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41. 发明授权

US06706581B1 Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices 失效
标题翻译：双栅电介质方案：用于高性能器件的SiON和低功率器件的高k
公开(公告)号：US06706581B1
公开(公告)日：2004-03-16
申请号：US10282387
申请日：2002-10-29
申请人： Tou-Hung Hou , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Shih-Chang Chen
发明人： Tou-Hung Hou , Ming-Fang Wang , Chi-Chun Chen , Chih-Wei Yang , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L218238
CPC分类号： H01L21/823456 , H01L21/823462
摘要： A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT
摘要翻译：描述了可扩展以满足对于50nm和70nm技术节点的要求的形成双栅极电介质层的方法。衬底具有分离器件区域的STI区域。界面层和高k电介质层依次沉积在衬底上。在一个器件区域上去除两个层，并且在暴露的器件区域上生长具有EOT <10nm的超薄氮氧化硅层。在SiON介电层的生长期间，高k电介质层退火。高k电介质层由金属氧化物或其硅酸盐或铝酸盐形成，并且能够以具有抑制的漏电流的EOT <1.8nm制造低功率器件。当形成多个栅极时，该方法与双重或三重氧化物厚度工艺兼容。

42. 发明授权

US06602799B2 Method of forming a uniform ultra-thin gate oxide layer 有权
公开(公告)号：US06602799B2
公开(公告)日：2003-08-05
申请号：US09954879
申请日：2001-09-17
申请人： Chi-Chun Chen , Wen Chang , Michael Chang , Shih-Chang Chen
发明人： Chi-Chun Chen , Wen Chang , Michael Chang , Shih-Chang Chen
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/02233 , H01L21/02255 , H01L21/02337 , H01L21/31662
摘要： A method of forming a highly uniform ultra-thin insulating gate oxide layer on a silicon wafer is presented where an oxide layer non-uniformity introduced at a processing temperature is compensated during a cooling step during which oxygen is added to give additional oxide layer growth thereby producing a substantially uniform oxide layer.

43. 发明授权

US08730992B2 System and method for transmitting network packets adapted for multimedia streams 有权
标题翻译：用于传输适用于多媒体流的网络分组的系统和方法
公开(公告)号：US08730992B2
公开(公告)日：2014-05-20
申请号：US12719020
申请日：2010-03-08
申请人： Chi-Chun Chen , Lung-Chih Kuo , Zhong-Zhen Wu
发明人： Chi-Chun Chen , Lung-Chih Kuo , Zhong-Zhen Wu
IPC分类号： H04L12/43 , H04L12/28
CPC分类号： H04L12/40013
摘要： A system and a method for transmitting network packets are provided. The system includes an information module, a scheduling module, and a forwarding module. The information module receives and records media information of a plurality of multimedia streams. The scheduling module calculates a guaranteed bit rate of each multimedia stream according to the media information provided by the information module, and rearranges isochronous packets of the multimedia streams in the first time slots of a plurality of clock cycles according to the guaranteed bit rates so that the transmission of the isochronous packets satisfies the guaranteed bit rates. The length of each clock cycle is a predetermined length. The length of the first time slot and the predetermined length are in a predetermined ratio. The forwarding module transmits all the packets of a clock cycle to a network at every a time interval of the predetermined length.
摘要翻译：提供了一种用于发送网络分组的系统和方法。该系统包括信息模块，调度模块和转发模块。信息模块接收并记录多个多媒体流的媒体信息。调度模块根据由信息模块提供的媒体信息来计算每个多媒体流的保证比特率，并且根据保证的比特率在多个时钟周期的第一时隙重新排列多媒体流的同步分组，使得同步分组的传输满足保证比特率。每个时钟周期的长度是预定的长度。第一时隙的长度和预定长度为预定比例。转发模块以预定长度的每个时间间隔将时钟周期的所有分组发送到网络。

44. 发明授权

US08658513B2 Isolation by implantation in LED array manufacturing 失效
标题翻译：通过植入在LED阵列制造中的隔离
公开(公告)号：US08658513B2
公开(公告)日：2014-02-25
申请号：US13098942
申请日：2011-05-02
申请人： Fareen Adeni Khaja , Deepak Ramappa , San Yu , Chi-Chun Chen
发明人： Fareen Adeni Khaja , Deepak Ramappa , San Yu , Chi-Chun Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/2654 , H01L21/26586 , H01L21/26593 , H01L21/266 , H01L27/156 , H01L33/0095 , H01L33/38
摘要： An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.
摘要翻译：公开了一种改进的LED阵列的制造方法。 p型层，多量子阱和n型层设置在基板上。然后将器件蚀刻以暴露n型层的部分。为了在相邻LED之间创建必要的电隔离，执行离子注入以产生非导电注入区域。在一些实施例中，注入区域延伸穿过p型层，MQW和n型层。在另一个实施例中，在n型层中形成第一注入区。此外，在p型层和紧邻蚀刻的n型层的多量子阱中产生第二注入区。在一些实施例中，垂直于衬底完成离子注入。在其他实施例中，以一定角度执行植入物。

45. 发明授权

US08502192B2 LED with uniform current spreading and method of fabrication 失效
标题翻译：具有均匀电流扩散的LED和制造方法
公开(公告)号：US08502192B2
公开(公告)日：2013-08-06
申请号：US12987655
申请日：2011-01-10
申请人： Joon Seop Kwak , Min Joo Park , Fareen Adeni Khaja , Chi-Chun Chen
发明人： Joon Seop Kwak , Min Joo Park , Fareen Adeni Khaja , Chi-Chun Chen
IPC分类号： H01L29/06 , H01L21/20 , H01L21/36
CPC分类号： H01L33/38 , H01L33/40
摘要： A lateral light emitting diode comprises a layer stack disposed on one side of a substrate, the layer stack including a p-type layer, n-type layer, and a p/n junction formed therebetween. The LED may further include a p-electrode disposed on a first side of the substrate and being in contact with the p-type layer on an exposed surface and an n-electrode disposed on the first side of the substrate and being in contact with an exposed surface of an n+ sub-layer of the n-type layer.
摘要翻译：横向发光二极管包括设置在基板的一侧上的层叠层，所述层堆叠包括p型层，n型层和在其间形成的p / n结。 LED还可以包括设置在基板的第一侧上的p电极，并且与暴露表面上的p型层和设置在基板的第一侧上的n电极接触，并且与 n型层的n +子层的露出面。

46. 发明授权

US08263422B2 Bond pad isolation and current confinement in an LED using ion implantation 失效
标题翻译：使用离子注入的LED中的焊盘隔离和电流限制
公开(公告)号：US08263422B2
公开(公告)日：2012-09-11
申请号：US13090301
申请日：2011-04-20
申请人： San Yu , Chi-Chun Chen
发明人： San Yu , Chi-Chun Chen
IPC分类号： H01L21/00
CPC分类号： H01L33/145
摘要： An improved method of creating LEDs is disclosed. Rather than using a dielectric coating to separate the bond pads from the top surface of the LED, this region of the LED is implanted with ions to increase its resistivity to minimize current flow therethrough. In another embodiment, a plurality of LEDs are produced on a single substrate by implanting ions in the regions between the LEDs and then etching a trench, where the trench is narrower than the implanted regions and positioned within these regions. This results in a trench where both sides have current confinement capabilities to reduce leakage.
摘要翻译：公开了一种改进的产生LED的方法。不是使用电介质涂层来将接合焊盘与LED的顶表面分离，所以LED的这个区域被注入离子以增加其电阻率以最小化通过其中的电流。在另一个实施例中，通过在LED之间的区域中注入离子然后蚀刻沟槽，在单个衬底上产生多个LED，其中沟槽比注入区域更窄并且位于这些区域内。这导致沟槽，其中两侧具有电流限制能力以减少泄漏。

47. 发明申请

US20120097918A1 IMPLANTED CURRENT CONFINEMENT STRUCTURE TO IMPROVE CURRENT SPREADING 审中-公开
标题翻译：加强目前的限制结构，以改善目前的扩张
公开(公告)号：US20120097918A1
公开(公告)日：2012-04-26
申请号：US13276790
申请日：2011-10-19
申请人： San YU , Chi-Chun Chen
发明人： San YU , Chi-Chun Chen
IPC分类号： H01L33/06 , H01L21/20
CPC分类号： H01L33/145
摘要： Ion implantation is used to form a current confinement structure, such as that in a light emitting diode. This current confinement structure defines multiple cells in one embodiment, each of which may surround an undoped region. The ion implantation may be performed between formation of the various layers. In one embodiment, the formation of one layer is interrupted and then resumed after ion implantation is performed.
摘要翻译：离子注入用于形成电流限制结构，例如在发光二极管中。该电流限制结构在一个实施例中定义了多个单元，每个单元可围绕未掺杂的区域。可以在各层的形成之间进行离子注入。在一个实施例中，中断一层的形成，然后在进行离子注入之后恢复。

48. 发明申请

US20090154472A1 Packet Forwarding Apparatus And Method For Virtualization Switch 有权
标题翻译：虚拟化交换机的分组转发设备及方法
公开(公告)号：US20090154472A1
公开(公告)日：2009-06-18
申请号：US12144632
申请日：2008-06-24
申请人： Yi-Cheng Chung , Stanley Lee , Yan-Hong Chiang , Chi-Chun Chen
发明人： Yi-Cheng Chung , Stanley Lee , Yan-Hong Chiang , Chi-Chun Chen
IPC分类号： H04L12/56
CPC分类号： H04L29/12858 , G06F3/0665 , G06F3/067 , H04L29/1233 , H04L61/25 , H04L61/6031 , H04L67/1097 , H04L69/22
摘要： Disclosed is a packet forwarding apparatus and method for virtualization switch, applicable to switch environments built by Internet Small Computer System Interface (iSCSI) connections. The packet forwarding apparatus comprises a header extractor, a dispatcher, and a forwarding unit. After completion of the authorization for iSCSI session connections, the header extractor receives at least an iSCSI packet and extracts the header for the at least an iSCSI packet. The dispatcher decides the flow directions for the received packets. The forwarding unit forwards the packets between the client-side connection and the storage-side connection, including converting the virtual address into physical address for the received iSCSI packets, building the mapping between the client-side interface and the storage-side interface, and delivering the payload associated with the connections.
摘要翻译：公开了一种适用于由互联网小型计算机系统接口（iSCSI）连接构建的交换环境的虚拟化交换机的分组转发装置和方法。分组转发装置包括报头提取器，分派器和转发单元。在完成iSCSI会话连接的授权之后，标题提取器至少接收一个iSCSI数据包，并提取至少一个iSCSI数据包的头文件。调度员决定接收到的数据包的流向。转发单元在客户端连接和存储侧连接之间转发数据包，包括将虚拟地址转换为接收到的iSCSI数据包的物理地址，构建客户端接口和存储侧接口之间的映射，以及提供与连接相关联的有效载荷。

49. 发明申请

US20070166904A1 Pre-gate dielectric process using hydrogen annealing 有权
标题翻译：使用氢退火的预栅电介质工艺
公开(公告)号：US20070166904A1
公开(公告)日：2007-07-19
申请号：US11333399
申请日：2006-01-17
申请人： Jocelyn Teo , Chi-Chun Chen , Shih-Chang Chen
发明人： Jocelyn Teo , Chi-Chun Chen , Shih-Chang Chen
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823828 , H01L21/823857
摘要： The preferred embodiment of the present invention provides a novel method of forming MOS devices using hydrogen annealing. The method includes providing a semiconductor substrate including a first region and a second region, forming at least a portion of a first MOS device covering at least a portion of the first active region, performing a hydrogen annealing in an ambient containing substantially pure hydrogen on the semiconductor substrate. The hydrogen annealing is performed after the step of the at least a portion of the first MOS device is formed, and preferably after a pre-oxidation cleaning. The method further includes forming a second MOS device in the second active region after hydrogen annealing. The hydrogen annealing causes the surface of the second active region to be substantially rounded, while the surface of the first active region is substantially flat.
摘要翻译：本发明的优选实施方案提供了使用氢退火形成MOS器件的新方法。该方法包括提供包括第一区域和第二区域的半导体衬底，形成覆盖第一有源区域的至少一部分的第一MOS器件的至少一部分，在包含基本上纯氢的环境中进行氢退火半导体衬底。氢退火在形成第一MOS器件的至少一部分的步骤之后，优选在预氧化清洗之后进行。该方法还包括在氢退火之后在第二有源区中形成第二MOS器件。氢退火使得第二有源区的表面基本上是圆形的，而第一有源区的表面基本上是平的。

50. 发明授权

US07166525B2 High temperature hydrogen annealing of a gate insulator layer to increase etching selectivity between conductive gate structure and gate insulator layer 有权
标题翻译：栅极绝缘体层的高温氢退火以增加导电栅极结构和栅极绝缘体层之间的蚀刻选择性
公开(公告)号：US07166525B2
公开(公告)日：2007-01-23
申请号：US10758317
申请日：2004-01-15
申请人： Vincent S. Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
发明人： Vincent S. Chang , Chia-Lin Chen , Chi-Chun Chen , Tze-Liang Lee , Shih-Chang Chen , Chien-Hao Chen
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28185 , H01L21/28202 , H01L21/3105 , H01L21/3144 , H01L21/32137 , H01L29/6659
摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.
摘要翻译：已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

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