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41. 发明授权

US07238580B2 Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration 有权
标题翻译：采用具有渐变杂质浓度的应力诱导源极漏极结构的半导体制造工艺
公开(公告)号：US07238580B2
公开(公告)日：2007-07-03
申请号：US11043577
申请日：2005-01-26
申请人： Marius K. Orlowski , Vance H. Adams , Chun-Li Liu , Matthew W. Stoker
发明人： Marius K. Orlowski , Vance H. Adams , Chun-Li Liu , Matthew W. Stoker
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： A semiconductor fabrication process has recessed stress-inducing source/drain (SISD) structures that are formed using a multiple phase formation process. The SISD structures are semiconductor structures having a lattice constant that differs from a lattice constant of the semiconductor substrate in which the source/drain structures are recessed. The SISD structures preferably include semiconductor compound having a first element (e.g., silicon) and a second element (e.g., germanium or carbon). The SISD structure has a composition gradient wherein the percentage of the second element varies from the upper surface of the source/drain structure to a lower surface of the SISD structure. The SISD structure may include a first layer with a first composition of the semiconductor compound underlying a second layer with a second composition of the semiconductor compound. The second layer may include an impurity and have a higher percentage of the second element that the first layer.
摘要翻译：半导体制造工艺具有使用多相形成工艺形成的凹陷的应力诱导源极/漏极（SISD）结构。 SISD结构是具有不同于源/漏结构凹陷的半导体衬底的晶格常数的晶格常数的半导体结构。 SISD结构优选包括具有第一元素（例如硅）和第二元素（例如锗或碳）的半导体化合物。 SISD结构具有组成梯度，其中第二元素的百分比从源极/漏极结构的上表面到SISD结构的下表面变化。 SISD结构可以包括具有半导体化合物的第一组成的第一层，位于第二层下面，半导体化合物的第二组成。第二层可以包括杂质，并且具有比第一层更高百分比的第二元素。

42. 发明授权

US07235847B2 Semiconductor device having a gate with a thin conductive layer 有权
标题翻译：具有具有薄导电层的栅极的半导体器件
公开(公告)号：US07235847B2
公开(公告)日：2007-06-26
申请号：US10944306
申请日：2004-09-17
申请人： Sinan Goktepeli , Alexander A. Demkov , Marius K. Orlowski
发明人： Sinan Goktepeli , Alexander A. Demkov , Marius K. Orlowski
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/42372
摘要： A semiconductor device (10) having a gate (16, 18 or 16, 18, 26, 28) with a thin conductive layer (18) is described. As the physical dimensions of semiconductor devices are scaled below the sub-micron regime, very thin gate dielectrics (16) are used. One problem encountered with very thin gate dielectrics is that the carriers can tunnel through the gate dielectric material, thus increasing the undesirable leakage current in the device. By using a thin layer for conductive layer (18), quantum confinement of carriers within conductive layer (18) can be induced. This quantum confinement removes modes which are propagating in the direction normal to the interfacial plane 15 from the Fermi level. Thus, the undesirable leakage current in the device (10) can be reduced. Additional conductive layers (e.g. 28) may be used to provide more carriers.
摘要翻译：描述了具有薄导电层（18）的栅极（16,18或16,18,26,28）的半导体器件（10）。由于半导体器件的物理尺寸缩小到亚微米级以下，所以使用非常薄的栅极电介质（16）。非常薄的栅极电介质遇到的一个问题是载流子可以穿过栅极电介质材料，从而增加器件中不希望的泄漏电流。通过使用用于导电层（18）的薄层，可以诱导导电层（18）内的载流子的量子限制。该量子限制去除了从费米能级垂直于界面15的方向传播的模式。因此，可以减少装置（10）中不期望的泄漏电流。附加的导电层（例如28）可用于提供更多的载体。

43. 发明授权

US07163903B2 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US07163903B2
公开(公告)日：2007-01-16
申请号：US10836172
申请日：2004-04-30
申请人： Marius K. Orlowski , Alexander L. Barr , Mariam G. Sadaka , Ted R. White
发明人： Marius K. Orlowski , Alexander L. Barr , Mariam G. Sadaka , Ted R. White
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供了具有硅层的半导体衬底。在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。在硅层上形成非晶或多晶硅锗层。或者，将锗注入硅层的顶部以形成非晶硅锗层。然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

44. 发明授权

US07029980B2 Method of manufacturing SOI template layer 有权
标题翻译：制造SOI模板层的方法
公开(公告)号：US07029980B2
公开(公告)日：2006-04-18
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/331
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

45. 发明授权

US08633515B2 Transistors with immersed contacts 有权
标题翻译：具有浸没触点的晶体管
公开(公告)号：US08633515B2
公开(公告)日：2014-01-21
申请号：US13613614
申请日：2012-09-13
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L29/41791 , H01L29/785 , H01L2029/7858
摘要： Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region. A contact extends into the first current electrode region and is electrically coupled to the first current electrode region.
摘要翻译：半导体结构的实施例包括第一电流电极区域，第二电流电极区域和沟道区域。沟道区域位于第一电流电极区域和第二电流电极区域之间，沟道区域位于半导体结构的鳍结构中。通道区域中的载流子传输通常在第一电流电极区域和第二电流电极区域之间的水平方向上。触点延伸到第一电流电极区域中并且电耦合到第一电流电极区域。

46. 发明授权

US07932189B2 Process of forming an electronic device including a layer of discontinuous storage elements 有权
标题翻译：形成包括不连续存储元件层的电子器件的工艺
公开(公告)号：US07932189B2
公开(公告)日：2011-04-26
申请号：US11627817
申请日：2007-01-26
申请人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
发明人： Tushar P. Merchant , Chun-Li Liu , Ramachandran Muralidhar , Marius K. Orlowski , Rajesh A. Rao , Matthew Stoker
IPC分类号： H01L21/31
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/11524 , H01L29/7887 , Y10S977/932 , Y10S977/943
摘要： An electronic device can include a layer of discontinuous storage elements. A dielectric layer overlying the discontinuous storage elements can be substantially hydrogen-free. A process of forming the electronic device can include forming a layer including silicon over the discontinuous storage elements. In one embodiment, the process includes oxidizing at least substantially all of the layer. In another embodiment, the process includes forming the layer using a substantially hydrogen-free silicon precursor material and oxidizing at least substantially all of the layer.
摘要翻译：电子设备可以包括不连续的存储元件层。覆盖不连续存储元件的电介质层可以是基本上无氢的。形成电子器件的工艺可以包括在不连续的存储元件上形成包括硅的层。在一个实施方案中，该方法包括至少基本上氧化所有该层。在另一个实施方案中，该方法包括使用基本上无氢的硅前体材料形成层并至少基本上全部氧化。

47. 发明授权

US07928502B2 Transistor devices with nano-crystal gate structures 有权
标题翻译：具有纳米晶体栅结构的晶体管器件
公开(公告)号：US07928502B2
公开(公告)日：2011-04-19
申请号：US12715947
申请日：2010-03-02
申请人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
发明人： Chun-Li Liu , Tushar P. Merchant , Marius K. Orlowski , Matthew W. Stoker
IPC分类号： H01L29/792 , H01L29/76
CPC分类号： H01L29/7883 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/66825 , H01L29/78
摘要： Embodiments of non-volatile semiconductor devices include a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric, and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
摘要翻译：非易失性半导体器件的实施例包括其中具有源极区域和漏极区域的衬底，所述源极区域和漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。栅极结构包括基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层，以及叠加在一个以上杂质阻挡层上的栅极导体层。可以使用最靠近栅极导体的阻挡层来调节器件的阈值电压和/或从栅极导体层延迟掺杂剂的扩散。

48. 发明授权

US07872311B2 Method and apparatus for mobility enhancement in a semiconductor device 有权
标题翻译：用于半导体器件中的移动性增强的方法和装置
公开(公告)号：US07872311B2
公开(公告)日：2011-01-18
申请号：US11857122
申请日：2007-09-18
申请人： Marius K. Orlowski , Suresh Venkatesan
发明人： Marius K. Orlowski , Suresh Venkatesan
IPC分类号： H01L29/76
CPC分类号： H01L29/7846 , H01L29/0653 , H01L29/1054 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/78687
摘要： A method and apparatus is presented that provides mobility enhancement in the channel region of a transistor. In one embodiment, a channel region (18) is formed over a substrate that is bi-axially stressed. Source (30) and drain (32) regions are formed over the substrate. The source and drain regions provide an additional uni-axial stress to the bi-axially stressed channel region. The uni-axial stress and the bi-axially stress are both compressive for P-channel transistors and tensile for N-channel transistors. Both transistor types can be included on the same integrated circuit.
摘要翻译：提出了一种在晶体管的沟道区域中提供迁移率增强的方法和装置。在一个实施例中，沟槽区域（18）形成在双轴向应力的衬底上。源极（30）和漏极（32）区域形成在衬底上。源极和漏极区域向双向应力通道区域提供额外的单轴应力。单向应力和双轴向应力对于P沟道晶体管是压缩的，对于N沟道晶体管是拉伸的。两种晶体管类型都可以包含在同一集成电路中。

49. 发明授权

US07781840B2 Semiconductor device structure 有权
标题翻译：半导体器件结构
公开(公告)号：US07781840B2
公开(公告)日：2010-08-24
申请号：US11742955
申请日：2007-05-01
申请人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

50. 发明申请

US20100190308A1 ELECTRONIC DEVICE INCLUDING A FIN-TYPE TRANSISTOR STRUCTURE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 有权
标题翻译：包括FIN型晶体管结构的电子器件和形成电子器件的工艺
公开(公告)号：US20100190308A1
公开(公告)日：2010-07-29
申请号：US12753226
申请日：2010-04-02
申请人： Marius K. Orlowski , James D. Burnett
发明人： Marius K. Orlowski , James D. Burnett
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译：电子器件可以包括绝缘层和鳍型晶体管结构。翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。电介质层和间隔结构可以位于半导体鳍片和栅电极之间。半导体鳍片可以包括沟道区域，其包括与位于与相对较低的VT相关联的部分和绝缘层之间的相对较高的VT相关联的部分。在一个实施例中，电源电压低于通道区域的相对较高的VT。还公开了一种用于形成电子器件的工艺。

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