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1. 发明授权

US07226833B2 Semiconductor device structure and method therefor 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US07226833B2
公开(公告)日：2007-06-05
申请号：US10977423
申请日：2004-10-29
申请人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L21/8234
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

2. 发明授权

US07029980B2 Method of manufacturing SOI template layer 有权
标题翻译：制造SOI模板层的方法
公开(公告)号：US07029980B2
公开(公告)日：2006-04-18
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
发明人： Chun-Li Liu , Marius K. Orlowski , Matthew W. Stoker , Philip J. Tobin , Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn G. Thomas , Ted R. White
IPC分类号： H01L21/331
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

3. 发明授权

US07781840B2 Semiconductor device structure 有权
标题翻译：半导体器件结构
公开(公告)号：US07781840B2
公开(公告)日：2010-08-24
申请号：US11742955
申请日：2007-05-01
申请人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
发明人： Ted R. White , Alexander L. Barr , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

4. 发明授权

US07037795B1 Low RC product transistors in SOI semiconductor process 有权
标题翻译： SOI半导体工艺中的低RC产品晶体管
公开(公告)号：US07037795B1
公开(公告)日：2006-05-02
申请号：US10965964
申请日：2004-10-15
申请人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
发明人： Alexander L. Barr , Olubunmi O. Adetutu , Bich-Yen Nguyen , Marius K. Orlowski , Mariam G. Sadaka , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/78618
摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
摘要翻译：半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。源极/漏极结构形成在沟槽内。源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

5. 发明授权

US07927956B2 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US07927956B2
公开(公告)日：2011-04-19
申请号：US11609664
申请日：2006-12-12
申请人： Marius K. Orlowski , Alexander L. Barr , Mariam G. Sadaka , Ted R. White
发明人： Marius K. Orlowski , Alexander L. Barr , Mariam G. Sadaka , Ted R. White
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供了具有硅层的半导体衬底。在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。在硅层上形成非晶或多晶硅锗层。或者，将锗注入硅层的顶部以形成非晶硅锗层。然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

6. 发明授权

US07163903B2 Method for making a semiconductor structure using silicon germanium 有权
标题翻译：使用硅锗制造半导体结构的方法
公开(公告)号：US07163903B2
公开(公告)日：2007-01-16
申请号：US10836172
申请日：2004-04-30
申请人： Marius K. Orlowski , Alexander L. Barr , Mariam G. Sadaka , Ted R. White
发明人： Marius K. Orlowski , Alexander L. Barr , Mariam G. Sadaka , Ted R. White
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/02126 , H01L21/02164 , H01L21/02236 , H01L21/31658 , H01L21/32105 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , Y10S438/933
摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.
摘要翻译：提供了具有硅层的半导体衬底。在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。在硅层上形成非晶或多晶硅锗层。或者，将锗注入硅层的顶部以形成非晶硅锗层。然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

7. 发明授权

US06831350B1 Semiconductor structure with different lattice constant materials and method for forming the same 有权
标题翻译：具有不同晶格常数材料的半导体结构及其形成方法
公开(公告)号：US06831350B1
公开(公告)日：2004-12-14
申请号：US10677844
申请日：2003-10-02
申请人： Chun-Li Liu , Alexander L. Barr , John M. Grant , Bich-Yen Nguyen , Marius K. Orlowski , Tab A. Stephens , Ted R. White , Shawn G. Thomas
发明人： Chun-Li Liu , Alexander L. Barr , John M. Grant , Bich-Yen Nguyen , Marius K. Orlowski , Tab A. Stephens , Ted R. White , Shawn G. Thomas
IPC分类号： H01L2930
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L29/04 , H01L29/665 , H01L29/7833
摘要： A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also disclosed.
摘要翻译：半导体结构包括具有第一晶格常数的第一松弛半导体材料的衬底。半导体器件层覆盖在衬底上，其中半导体器件层包括具有不同于第一晶格常数的第二晶格常数的第二松弛半导体材料。此外，介电层介于基板和半导体器件层之间，其中介电层包括设置在电介质层内的编程过渡区，用于在第一晶格常数和第二晶格常数之间转变。编程的过渡区域包括多个层，多个层中相邻的层具有不同的晶格常数，其中相邻的层之一具有超过形成缺陷所需的第一临界厚度的第一厚度，而另一层具有第二厚度不超过第二临界厚度。多个层中的每个相邻层形成用于促进过渡区中的缺陷迁移到并终止于编程的过渡区的边缘的界面。还公开了制备该方法的方法。

8. 发明申请

US20070281446A1 Dual surface SOI by lateral epitaxial overgrowth 有权
标题翻译：通过横向外延过度生长的双面SOI
公开(公告)号：US20070281446A1
公开(公告)日：2007-12-06
申请号：US11443627
申请日：2006-05-31
申请人： Brian A. Winstead , Omar Zia , Mariam G. Sadaka , Marius K. Orlowski
发明人： Brian A. Winstead , Omar Zia , Mariam G. Sadaka , Marius K. Orlowski
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/785
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.
摘要翻译：半导体工艺和装置通过在第一区域（99）中暴露掩埋氧化物层（80）来提供平坦化的混合衬底（18），选择性地蚀刻掩埋氧化物层（80）以暴露第一半导体层第二较小种子区域（98），然后从填充第二沟槽开口（100）的第一半导体层（70）的种子区域（98）外延生长第一外延半导体材料，并在暴露的绝缘体层上横向生长 80）以填充第一沟槽开口（99）的至少一部分，从而形成与第二半导体层（90）电隔离的第一外延半导体层（101）。通过使用沉积的（100）硅并在外延生长（110）硅层（101）上形成第一SOI晶体管（161）在第一SOI层（90）上形成第一SOI晶体管器件（160），高性能CMOS器件获得。

9. 发明授权

US07435639B2 Dual surface SOI by lateral epitaxial overgrowth 有权
标题翻译：通过横向外延过度生长的双面SOI
公开(公告)号：US07435639B2
公开(公告)日：2008-10-14
申请号：US11443627
申请日：2006-05-31
申请人： Brian A. Winstead , Omar Zia , Mariam G. Sadaka , Marius K. Orlowski
发明人： Brian A. Winstead , Omar Zia , Mariam G. Sadaka , Marius K. Orlowski
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/785
摘要： A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.
摘要翻译：半导体工艺和装置通过在第一区域（99）中暴露掩埋氧化物层（80）来提供平坦化的混合衬底（18），选择性地蚀刻掩埋氧化物层（80）以暴露第一半导体层第二较小种子区域（98），然后从填充第二沟槽开口（100）的第一半导体层（70）的种子区域（98）外延生长第一外延半导体材料，并在暴露的绝缘体层上横向生长 80）以填充第一沟槽开口（99）的至少一部分，从而形成与第二半导体层（90）电隔离的第一外延半导体层（101）。通过使用沉积的（100）硅并在外延生长（110）硅层（101）上形成第一SOI晶体管（161）在第一SOI层（90）上形成第一SOI晶体管器件（160），高性能CMOS器件获得。

10. 发明授权

US07354814B2 Semiconductor process with first transistor types oriented in a first plane and second transistor types oriented in a second plane 有权
标题翻译：在第一平面中定向的第一晶体管类型的半导体工艺和在第二平面中定向的第二晶体管类型
公开(公告)号：US07354814B2
公开(公告)日：2008-04-08
申请号：US10949057
申请日：2004-09-23
申请人： Marius K. Orlowski , Bich-Yen Nguyen
发明人： Marius K. Orlowski , Bich-Yen Nguyen
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/823807 , H01L21/823885 , H01L27/0922 , H01L29/78642 , H01L29/78687
摘要： A semiconductor fabrication process includes forming a recess in a semiconductor substrate. A silicon germanium film is formed on a sidewall of the recess. A gate dielectric and gate electrode are formed adjacent the silicon germanium film. Source/drain regions are then formed wherein a first source/drain region is adjacent a first side of the gate electrode in an upper surface of the substrate and a second source/drain region adjacent a second side of the gate electrode is below a lower surface of the recess. Etching the exposed portion of the substrate may be done so as to form a rounded corner at the junction of the recess sidewall and the recess lower surface. The silicon germanium film formation is preferably epitaxial. An epitaxial silicon film may be formed adjacent the silicon germanium film.
摘要翻译：半导体制造工艺包括在半导体衬底中形成凹部。在该凹槽的侧壁上形成硅锗膜。在硅锗膜附近形成栅极电介质和栅电极。然后形成源极/漏极区，其中第一源极/漏极区在衬底的上表面中与栅电极的第一侧相邻，并且与栅电极的第二侧相邻的第二源极/漏极区在下表面的凹陷。可以对衬底的暴露部分进行蚀刻，以便在凹陷侧壁和凹陷下表面的接合处形成圆角。硅锗膜的形成优选是外延的。可以在硅锗膜附近形成外延硅膜。

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