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41. 发明授权

US07227258B2 Mounting structure in integrated circuit module 失效
标题翻译：集成电路模块中的安装结构
公开(公告)号：US07227258B2
公开(公告)日：2007-06-05
申请号：US10988390
申请日：2004-11-12
申请人： Jeong-Hyeon Cho , Byung-Se So , Jin-Kyu Chang
发明人： Jeong-Hyeon Cho , Byung-Se So , Jin-Kyu Chang
IPC分类号： H01L23/34
CPC分类号： H05K1/181 , H01L2924/0002 , H05K2201/097 , H05K2201/10378 , H05K2201/10515 , H05K2201/10734 , Y02P70/611 , H01L2924/00
摘要： Embodiments of the present invention may include an integrated circuit module structure for a high-density mounting. An embodiment may include a wiring board, having a mounting space with a mounting length determined in a first direction and a mounting width determined in a second direction, on at least one surface thereof, and a plurality of integrated circuit packages having a package mounting combination length longer than the mounting length of the wiring board. An embodiment may also have some packages among the plurality of integrated circuit packages mounted directly on the mounting space, while other packages are mounted indirectly on the mounting space. The present embodiment may have packages that are overlapped horizontally and vertically distant from one another. Embodiments allow a plurality of chips or packages to be mounted in a limited area without changing a form factor of integrated circuit module even when integrated circuit chip or package size increases.
摘要翻译：本发明的实施例可以包括用于高密度安装的集成电路模块结构。一个实施例可以包括布线板，具有在其至少一个表面上具有在第一方向上确定的安装长度和在第二方向上确定的安装宽度的安装空间的安装空间以及具有封装安装组合的多个集成电路封装长度比布线板的安装长度长。实施例还可以在直接安装在安装空间上的多个集成电路封装中具有一些封装，而其他封装间接安装在安装空间上。本实施例可以具有水平和垂直地彼此重叠的封装。即使在集成电路芯片或封装尺寸增加时，实施例允许多个芯片或封装被安装在有限的区域中而不改变集成电路模块的外形尺寸。

42. 发明申请

US20060069948A1 Error detecting memory module and method 审中-公开
标题翻译：检测内存模块和方法错误
公开(公告)号：US20060069948A1
公开(公告)日：2006-03-30
申请号：US11181059
申请日：2005-07-13
申请人： Jong-Cheol Seo , Byung-Se So , Young-Man Ahn
发明人： Jong-Cheol Seo , Byung-Se So , Young-Man Ahn
IPC分类号： G06F11/00
CPC分类号： G11B20/1833 , G06F11/1016 , G11B2020/1823 , G11B2220/60
摘要： We describe and claim an error detecting memory module and method. The module comprises a plurality of memory devices, each memory device to receive an address signal and a command signal from a memory controller, and to detect an error in the address and command signals responsive to an input parity signal. In an embodiment, each memory device is adapted to provide an output parity signal to the memory controller responsive to the detection.
摘要翻译：我们描述和声明一个错误检测内存模块和方法。该模块包括多个存储器件，每个存储器件用于从存储器控制器接收地址信号和命令信号，以及响应于输入奇偶校验信号来检测地址和命令信号中的错误。在一个实施例中，每个存储器件适于响应于检测而向存储器控制器提供输出奇偶校验信号。

43. 发明申请

US20060044927A1 Memory module, memory unit, and hub with non-periodic clock and methods of using the same 失效
公开(公告)号：US20060044927A1
公开(公告)日：2006-03-02
申请号：US11029008
申请日：2005-01-05
申请人： You-Keun Han , Hui-Chong Shin , Seung-Jin Seo , Byung-Se So , Young-Man Ahn , Seung-Man Shin , Jung-Kuk Lee , Ho-Suk Lee
发明人： You-Keun Han , Hui-Chong Shin , Seung-Jin Seo , Byung-Se So , Young-Man Ahn , Seung-Man Shin , Jung-Kuk Lee , Ho-Suk Lee
IPC分类号： G11C8/02
CPC分类号： G11C5/04 , G06F13/1689 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/401 , G11C29/12015 , G11C29/14
摘要： A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.

44. 发明申请

US20050212551A1 Memory module system with efficient control of on-die termination 有权
标题翻译：内存模块系统，具有对片上终端的高效控制
公开(公告)号：US20050212551A1
公开(公告)日：2005-09-29
申请号：US10997406
申请日：2004-11-24
申请人： Byung-Se So , Jeong-Hyeon Cho , Jae-Jun Lee
发明人： Byung-Se So , Jeong-Hyeon Cho , Jae-Jun Lee
IPC分类号： G06F12/00 , G11C5/00 , G11C7/10 , G11C11/401 , H03K19/003 , H04L25/02
CPC分类号： H04L25/0278 , G11C5/04 , G11C7/1078 , G11C7/1084
摘要： For ODT (on-die termination) control within a memory module system, just one pin from the memory controller is used for sending command signals indicating an activated one of the memory devices. The activated memory device includes components that are turned on for generating the ODT control signal for controlling an ODT circuit of inactivated memory device(s). The components for generating an ODT control signal within the inactivated memory devices are turned off for minimized power consumption.
摘要翻译：对于存储器模块系统内的ODT（片上终端）控制，仅使用来自存储器控制器的一个引脚来发送指示已激活的存储器件的命令信号。激活的存储器件包括被开启以产生用于控制非激活存储器件的ODT电路的ODT控制信号的组件。用于在非激活的存储器件内产生ODT控制信号的组件被关闭以最小化功率消耗。

45. 发明申请

US20050089106A1 Data transmission system and method 失效
标题翻译：数据传输系统及方法
公开(公告)号：US20050089106A1
公开(公告)日：2005-04-28
申请号：US10913359
申请日：2004-08-09
申请人： Jeong-Hyeon Cho , Jae-Jun Lee , Jong-Hoon Kim , Byung-Se So
发明人： Jeong-Hyeon Cho , Jae-Jun Lee , Jong-Hoon Kim , Byung-Se So
IPC分类号： H04B3/50 , H04L25/14 , H04B1/69
CPC分类号： H04L25/14
摘要： A data transmission system and method characterized by the use of multiple differential output amplifiers to transmits differential data signals that vary in accordance with control signals derived from a reference data output strobe signal, and multiple differential amplifiers to receive the differential data signals and detect such variations to generate a data input strobe signal corresponding to the data output strobe signal.
摘要翻译：一种数据传输系统和方法，其特征在于使用多个差分输出放大器来传输根据从参考数据输出选通信号导出的控制信号而变化的差分数据信号，以及多个差分放大器以接收差分数据信号并检测这些变化以产生对应于数据输出选通信号的数据输入选通信号。

46. 发明申请

US20050023560A1 Memory module test system 失效
标题翻译：内存模块测试系统
公开(公告)号：US20050023560A1
公开(公告)日：2005-02-03
申请号：US10900140
申请日：2004-07-28
申请人： Young-Man Ahn , Byung-Se So , Seung-Jin Seo , Seung-Man Shin
发明人： Young-Man Ahn , Byung-Se So , Seung-Jin Seo , Seung-Man Shin
IPC分类号： G11C29/00 , H04L12/413
CPC分类号： G11C29/56 , G11C5/04 , G11C29/48 , G11C29/56012 , G11C2029/5602
摘要： A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.
摘要翻译：一种包括至少一个存储器模块的存储器模块测试系统。所述至少一个存储器模块包括第一集线器和多个半导体存储器件。该系统包括用于测试至少一个存储器模块的测试器。第二集线器位于第一集线器和测试仪之间。第二集线器用于将从测试器输出的存储器命令和存储器数据转换成分组数据，并将分组数据发送到第一集线器。第二集线器将从第一集线器输出的分组数据转换为存储器数据，并将存储器数据发送到测试器。

47. 发明申请

US20050010841A1 Memory module and method of testing the same 有权
标题翻译：内存模块和测试方法相同
公开(公告)号：US20050010841A1
公开(公告)日：2005-01-13
申请号：US10831702
申请日：2004-04-23
申请人： Jung-Bae Lee , Hoe-Ju Chung , Byung-Se So
发明人： Jung-Bae Lee , Hoe-Ju Chung , Byung-Se So
IPC分类号： G11C7/10 , G11C29/14 , G11C29/48 , G11C29/00
CPC分类号： G11C29/14 , G11C11/401 , G11C29/1201 , G11C29/48 , G11C2029/2602
摘要： The present invention provides a memory module, comprising: a plurality of semiconductor memory devices for writing and reading m-bit parallel data; and a buffer for converting n-bit serial data into the m-bit parallel data to output to the plurality of semiconductor memory devices, converting the m-bit parallel data into the n-bit serial data to output to a first external portion during a normal operation, buffering 2n-bit parallel data to output to the plurality of semiconductor memory devices, and buffering the m-bit parallel data to output to a second external portion during a test operation.
摘要翻译：本发明提供了一种存储器模块，包括：用于写入和读取m位并行数据的多个半导体存储器件; 以及用于将n位串行数据转换成m位并行数据以输出到多个半导体存储器件的缓冲器，将m位并行数据转换成n位串行数据，以在第一外部部分输出正常操作，缓冲2n位并行数据以输出到多个半导体存储器件，以及在测试操作期间缓冲m位并行数据以输出到第二外部部分。

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