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41. 发明申请

US20090201626A1 GAP CAPACITORS FOR MONITORING STRESS IN SOLDER BALLS IN FLIP CHIP TECHNOLOGY 失效
标题翻译：用于监测飞利浦芯片技术中焊接棒应力的GAP电容器
公开(公告)号：US20090201626A1
公开(公告)日：2009-08-13
申请号：US12028845
申请日：2008-02-11
申请人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Stephen P. Ayotte , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
IPC分类号： H01G4/228 , H01L21/20
CPC分类号： H01L23/5223 , H01L22/34 , H01L24/02 , H01L24/11 , H01L28/60 , H01L2224/0401 , H01L2224/1147 , H01L2224/13099 , H01L2224/16 , H01L2224/29116 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/30105 , Y10S438/957 , H01L2924/00
摘要： A semiconductor structure and a method for forming the same. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball.
摘要翻译：半导体结构及其形成方法。该结构包括（i）电介质层，（ii）电介质层上的底部电容器板和导电线，（iii）底部电容器板顶部的顶部电容器板，（iv）间隙区域，以及（v）电介质层上的焊球。电介质层包括限定垂直于顶表面的参考方向的顶表面。顶部电容器板在底部电容器板上沿参考方向重叠。间隙区域夹在底部电容器板和顶部电容器板之间。间隙区域不包括任何液体或固体材料。焊球与导电线电连接。顶部电容器板设置在电介质层和焊球之间。

42. 发明申请

US20090179284A1 SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS, METAL GATE ELECTRODE REGIONS, AND LOW FRINGING CAPACITANCES 失效
标题翻译：具有高K栅电介质层，金属栅电极区和低边界电容的半导体晶体管
公开(公告)号：US20090179284A1
公开(公告)日：2009-07-16
申请号：US12013514
申请日：2008-01-14
申请人： Jeffrey Peter Gambino
发明人： Jeffrey Peter Gambino
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4966 , H01L29/518 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A semiconductor structure and a method for forming the same. The structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a gate dielectric region, and (iv) a gate electrode region, (v) a plurality of interconnect layers on the gate electrode region, and (vi) first and second spaces. The gate dielectric region is disposed between and in direct physical contact with the channel region and the gate electrode region. The gate electrode region is disposed between and in direct physical contact with the gate dielectric region and the interconnect layers. The first and second spaces are in direct physical contact with the gate electrode region. The first space is disposed between the first source/drain region and the gate electrode region. The second space is disposed between the second source/drain region and the gate electrode region.
摘要翻译：半导体结构及其形成方法。该结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）栅极电介质区，和（iv）栅电极区，（v）栅电极区上的多个互连层，以及（vi）第一和第二空间。栅极电介质区域设置在沟道区域和栅电极区域之间并与其直接物理接触。栅电极区域设置在栅极电介质区域和互连层之间并与其直接物理接触。第一和第二空间与栅电极区域直接物理接触。第一空间设置在第一源极/漏极区域和栅极电极区域之间。第二空间设置在第二源极/漏极区域和栅极电极区域之间。

43. 发明申请

US20080308948A1 WAFER-TO-WAFER ALIGNMENTS 失效
标题翻译： WAFER-WAFER对准
公开(公告)号：US20080308948A1
公开(公告)日：2008-12-18
申请号：US12198221
申请日：2008-08-26
申请人： Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人： Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
IPC分类号： H01L23/52 , H01L21/66
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译：用于对准晶片的结构及其操作方法。该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。第一和第二半导体晶片经由公共表面彼此直接物理接触。如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。第一个方向基本上平行于共同的表面。

44. 发明申请

US20080261121A1 PHOTOLITHOGRAPHY MASK WITH PROTECTIVE SILICIDE CAPPING LAYER 审中-公开
标题翻译：具有保护性硅胶覆盖层的光刻胶面板
公开(公告)号：US20080261121A1
公开(公告)日：2008-10-23
申请号：US11738004
申请日：2007-04-20
申请人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
发明人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30 , G03F1/48 , G03F1/54
摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.
摘要翻译：光掩模和制造光掩模的方法。所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。保形层通过氧化形成。

45. 发明申请

US20080261120A1 PHOTOLITHOGRAPHY MASK WITH INTEGRALLY FORMED PROTECTIVE CAPPING LAYER 审中-公开
标题翻译：具有整体形成的保护层的光刻胶面板
公开(公告)号：US20080261120A1
公开(公告)日：2008-10-23
申请号：US11737956
申请日：2007-04-20
申请人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
发明人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30 , G03F1/48 , G03F1/54
摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.
摘要翻译：光掩模和制造光掩模的方法。所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。保形层通过氧化形成。

46. 发明授权

US07193423B1 Wafer-to-wafer alignments 有权
标题翻译：晶圆对晶圆对准
公开(公告)号：US07193423B1
公开(公告)日：2007-03-20
申请号：US11275112
申请日：2005-12-12
申请人： Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人： Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
IPC分类号： G01R27/26 , G01R31/02
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译：用于对准晶片的结构及其操作方法。该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。第一和第二半导体晶片经由公共表面彼此直接物理接触。如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。第一个方向基本上平行于共同的表面。

47. 发明授权

US06326260B1 Gate prespacers for high density, high performance DRAMs 失效
标题翻译：用于高密度，高性能DRAM的Gate Prepacers
公开(公告)号：US06326260B1
公开(公告)日：2001-12-04
申请号：US09599703
申请日：2000-06-22
申请人： Ramachandra Divakaruni , James William Adkisson , Mary Elizabeth Weybright , Scott Halle , Jeffrey Peter Gambino , Heon Lee
发明人： Ramachandra Divakaruni , James William Adkisson , Mary Elizabeth Weybright , Scott Halle , Jeffrey Peter Gambino , Heon Lee
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823462 , H01L27/10873
摘要： A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer. Specifically, the structure comprises a semiconductor substrate having a gate oxide layer formed thereon, said substrate including array regions and support regions, said array regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer formed on said conductor material layer, said nitride cap layer and said conductor material layer having spacers formed on sidewalls thereof and said polysilicon layer having an array oxide layer formed on sidewalls thereof, said spacers being substantially flush with the oxide sidewalls, said support regions include at least one patterned gate conductor, said patterned gate conductor having a polysilicon layer formed on said gate oxide layer, a conductor material layer formed on said polysilicon layer, and a nitride cap layer on said conductor material layer, said polysilicon layer having a support oxide layer formed on sidewalls thereof, wherein said array oxide layer has a thickness that is greater than said support oxide layer.
摘要翻译：提供了一种存储器件结构，其中阵列氧化物层的厚度大于支撑氧化物层的厚度。具体地，该结构包括其上形成有栅极氧化层的半导体衬底，所述衬底包括阵列区域和支撑区域，所述阵列区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层形成在所述多晶硅层上的导体材料层和形成在所述导体材料层上的氮化物覆盖层，所述氮化物覆盖层和所述导体材料层具有形成在其侧壁上的隔离物，并且所述多晶硅层具有形成在侧壁上的阵列氧化物层所述间隔件与氧化物侧壁基本齐平，所述支撑区域包括至少一个图案化栅极导体，所述图案化栅极导体具有形成在所述栅极氧化物层上的多晶硅层，形成在所述多晶硅层上的导体材料层，以及所述多晶硅层在所述导体材料层上形成氮化物覆盖层形成在其侧壁上的支撑氧化物层，其中所述阵列氧化物层的厚度大于所述支撑氧化物层。

48. 发明授权

US06261914B1 Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer 失效
标题翻译：使用自对准抛光速率增强层改善化学机械抛光的局部均匀性的方法
公开(公告)号：US06261914B1
公开(公告)日：2001-07-17
申请号：US09361961
申请日：1999-07-27
申请人： Ramachandra Divakaruni , Jeffrey Peter Gambino , Carl J. Radens , Jeremy K. Stephens
发明人： Ramachandra Divakaruni , Jeffrey Peter Gambino , Carl J. Radens , Jeremy K. Stephens
IPC分类号： H01L21331
CPC分类号： H01L21/31053 , H01L21/76229
摘要： A method for making a semiconductor device, includes forming an oxide layer on a silicon substrate, forming a nitride layer over the oxide layer; depositing one of a doped oxide layer and an undoped porous oxide layer on the nitride layer, etching trenches through the one of the doped layer and the undoped porous oxide layer, the nitride layer, and the oxide layer, depositing an undoped oxide layer to fill the trenches, and patterning the undoped oxide by chemical mechanical polishing (CMP).
摘要翻译：一种制造半导体器件的方法，包括在硅衬底上形成氧化物层，在所述氧化物层上形成氮化物层; 在氮化物层上沉积掺杂氧化物层和未掺杂的多孔氧化物层之一，蚀刻通过掺杂层和未掺杂的多孔氧化物层，氮化物层和氧化物层之一的沟槽，沉积未填充的氧化物层以填充沟槽，并通过化学机械抛光（CMP）图案化未掺杂的氧化物。

49. 发明授权

US08647913B2 Image sensor, method and design structure including non-planar reflector 失效
标题翻译：图像传感器，方法和设计结构包括非平面反射器
公开(公告)号：US08647913B2
公开(公告)日：2014-02-11
申请号：US13614210
申请日：2012-09-13
申请人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
发明人： James William Adkisson , Jeffrey Peter Gambino , Robert Kenneth Leidy , John J. Ellis-Monaghan
IPC分类号： H01L27/00
CPC分类号： H01L27/14643 , H01L27/14621 , H01L27/14625 , H01L27/1464 , H01L27/14683 , H01L27/14685
摘要： A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.
摘要翻译：固态图像传感器，制造固态图像传感器的方法和用于制造固态图像传感器结构的设计结构包括依次包括感光区域的基板。还包括在固态图像传感器内的非平面反射器层位于感光区域和基板的与感光区域和基板的入射辐射侧相对的一侧上。非平面反射器层被成形和定位成将未捕获的入射辐射反射回光敏区域，同时避免与衬底内横向分离的附加光敏区域的光学串扰。

50. 发明授权

US08238032B2 Variable focus point lens 有权
标题翻译：可变焦点镜头
公开(公告)号：US08238032B2
公开(公告)日：2012-08-07
申请号：US12708561
申请日：2010-02-19
申请人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Kirk David Peterson , Jed Hickory Rankin
发明人： John Joseph Ellis-Monaghan , Jeffrey Peter Gambino , Kirk David Peterson , Jed Hickory Rankin
IPC分类号： G02B3/12
CPC分类号： G02B3/14
摘要： A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.
摘要翻译：可变焦点透镜包括透明容器，透明容器包括透明的外壳，该透明外壳包含将透明容器的内部容积分隔成上部容器部分和下部容器部分的透明柔性膜。上罐部分和下罐部分含有不同折射率的液体。透明柔性膜被静电移位以改变光路中的第一罐部分和第二罐部分的厚度，从而轴向和/或横向地移动透镜的焦点。膜的静电位移可以通过膜中的固定电荷和透明外壳上的封闭侧导电结构阵列，或透明膜上的膜侧导电结构阵列和外壳侧阵列导电结构。

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