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1. 发明授权

US07193423B1 Wafer-to-wafer alignments 有权
标题翻译：晶圆对晶圆对准
公开(公告)号：US07193423B1
公开(公告)日：2007-03-20
申请号：US11275112
申请日：2005-12-12
申请人： Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人： Timothy Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
IPC分类号： G01R27/26 , G01R31/02
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译：用于对准晶片的结构及其操作方法。该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。第一和第二半导体晶片经由公共表面彼此直接物理接触。如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。第一个方向基本上平行于共同的表面。

2. 发明授权

US08004289B2 Wafer-to-wafer alignments 失效
标题翻译：晶圆对晶圆对准
公开(公告)号：US08004289B2
公开(公告)日：2011-08-23
申请号：US12198221
申请日：2008-08-26
申请人： Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人： Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
IPC分类号： G01R27/26 , G01R31/308
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译：用于对准晶片的结构及其操作方法。该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。第一和第二半导体晶片经由公共表面彼此直接物理接触。如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。第一个方向基本上平行于共同的表面。

3. 发明申请

US20080308948A1 WAFER-TO-WAFER ALIGNMENTS 失效
标题翻译： WAFER-WAFER对准
公开(公告)号：US20080308948A1
公开(公告)日：2008-12-18
申请号：US12198221
申请日：2008-08-26
申请人： Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人： Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Stephen Ellinwood Luce , Edmund Juris Sprogis
IPC分类号： H01L23/52 , H01L21/66
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译：用于对准晶片的结构及其操作方法。该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。第一和第二半导体晶片经由公共表面彼此直接物理接触。如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。第一个方向基本上平行于共同的表面。

4. 发明授权

US07474104B2 Wafer-to-wafer alignments 失效
标题翻译：晶圆对晶圆对准
公开(公告)号：US07474104B2
公开(公告)日：2009-01-06
申请号：US11557668
申请日：2006-11-08
申请人： Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffee , Stephen Ellinwood Luce , Edmund Juris Sprogis
发明人： Thomas Joseph Dalton , Jeffrey Peter Gambino , Mark David Jaffee , Stephen Ellinwood Luce , Edmund Juris Sprogis
IPC分类号： G01R27/26 , H01L23/544
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译：用于对准晶片的结构及其操作方法。该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。第一和第二半导体晶片经由公共表面彼此直接物理接触。如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。第一个方向基本上平行于共同的表面。

5. 发明申请

US20080261122A1 PHOTOLITHOGRAPHY MASK WITH PROTECTIVE CAPPING LAYER 审中-公开
标题翻译：具有保护层的光刻胶面
公开(公告)号：US20080261122A1
公开(公告)日：2008-10-23
申请号：US11738070
申请日：2007-04-20
申请人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
发明人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30 , G03F1/48 , G03F1/54
摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and a top surface; the non-printable region comprising a second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and a top surface; and a capping layer on the sidewalls of the first opaque regions and the sidewalls of the second opaque region.
摘要翻译：光掩模和制造光掩模的方法。所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和顶表面; 所述不可打印区域包括在所述基板的顶表面上方升高的第二不透明区域，所述第二不透明区域具有侧壁和顶表面; 以及在第一不透明区域的侧壁和第二不透明区域的侧壁上的覆盖层。

6. 发明授权

US07348210B2 Post bump passivation for soft error protection 有权
标题翻译：后凸钝化用于软错误保护
公开(公告)号：US07348210B2
公开(公告)日：2008-03-25
申请号：US10908084
申请日：2005-04-27
申请人： Timothy H. Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter , Edmund Juris Sprogis
发明人： Timothy H. Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter , Edmund Juris Sprogis
IPC分类号： H01L21/00
CPC分类号： H01L23/556 , H01L24/02 , H01L24/11 , H01L24/12 , H01L2224/0401 , H01L2224/05572 , H01L2224/13022 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/00 , H01L2924/00014
摘要： A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.
摘要翻译：一种结构及其形成方法。该方法包括（a）提供一种结构，其包括（i）电介质层，（ii）与电介质层顶表面直接物理接触的导电接合焊盘，（iii）介电层上的第一钝化层其中所述第一钝化层包括位于所述导电接合焊盘正上方的第一孔，以及（iv）填充所述第一孔并电耦合到所述导电接合焊盘的导电焊料凸块; 以及（b）在所述第一钝化层上形成第二钝化层，其中第二钝化层与所述导电焊料凸块直接物理接触，并且其中所述导电焊料凸点在所述第二钝化层形成所述第二钝化层之后立即暴露于周围环境执行钝化层。

7. 发明申请

US20080261121A1 PHOTOLITHOGRAPHY MASK WITH PROTECTIVE SILICIDE CAPPING LAYER 审中-公开
标题翻译：具有保护性硅胶覆盖层的光刻胶面板
公开(公告)号：US20080261121A1
公开(公告)日：2008-10-23
申请号：US11738004
申请日：2007-04-20
申请人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
发明人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30 , G03F1/48 , G03F1/54
摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.
摘要翻译：光掩模和制造光掩模的方法。所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。保形层通过氧化形成。

8. 发明申请

US20080261120A1 PHOTOLITHOGRAPHY MASK WITH INTEGRALLY FORMED PROTECTIVE CAPPING LAYER 审中-公开
标题翻译：具有整体形成的保护层的光刻胶面板
公开(公告)号：US20080261120A1
公开(公告)日：2008-10-23
申请号：US11737956
申请日：2007-04-20
申请人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
发明人： Jeffrey Peter Gambino , Robert Kenneth Leidy , Kirk David Peterson , Jed Hickory Rankin , Edmund Juris Sprogis
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/30 , G03F1/48 , G03F1/54
摘要： A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.
摘要翻译：光掩模和制造光掩模的方法。所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。保形层通过氧化形成。

9. 发明授权

US07678696B2 Method of making through wafer vias 有权
标题翻译：通过晶片通孔制作方法
公开(公告)号：US07678696B2
公开(公告)日：2010-03-16
申请号：US12188230
申请日：2008-08-08
申请人： Paul Stephen Andry , Edmund Juris Sprogis , Cornelia Kang-I Tsang
发明人： Paul Stephen Andry , Edmund Juris Sprogis , Cornelia Kang-I Tsang
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench.
摘要翻译：制造通过晶片通孔的方法。该方法包括：在半导体衬底中形成沟槽，沟槽通向衬底的顶表面; 在沟槽的侧壁和底部上形成多晶硅层; 氧化多晶硅层以将多晶硅层转变成沟槽的侧壁和底部上的氧化硅层，氧化硅层不填充沟槽; 用电导体填充沟槽中的剩余空间; 以及从衬底的底表面使衬底细化并从沟槽的底部去除氧化硅层。该方法还可以包括在填充沟槽之前在氧化硅层上形成金属层。

10. 发明授权

US06294406B1 Highly integrated chip-on-chip packaging 有权
标题翻译：高度集成的片上芯片封装
公开(公告)号：US06294406B1
公开(公告)日：2001-09-25
申请号：US09350274
申请日：1999-07-06
申请人： Claude Louis Bertin , Thomas George Ference , Wayne John Howell , Edmund Juris Sprogis
发明人： Claude Louis Bertin , Thomas George Ference , Wayne John Howell , Edmund Juris Sprogis
IPC分类号： H01L2144
CPC分类号： H01L25/0657 , H01L24/73 , H01L24/97 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73207 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06541 , H01L2225/06555 , H01L2225/06572 , H01L2225/06586 , H01L2924/01322 , H01L2924/07811 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/00014 , H01L2924/00 , H01L2924/00012 , H01L2224/81
摘要： The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry.
摘要翻译：本发明的优点通过具有至少两个完全功能的芯片，电连接在一起的片上芯片模块和用于将全功能芯片电连接到外部电路的片上芯片组件连接/互连来实现。

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