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41. 发明授权

US5555744A Refrigerant circuit for ice making machines etc. 失效
标题翻译：制冰机制冷剂回路等
公开(公告)号：US5555744A
公开(公告)日：1996-09-17
申请号：US386682
申请日：1995-02-10
申请人： Akihiko Hirano
发明人： Akihiko Hirano
IPC分类号： F25B47/02 , F25C5/10
CPC分类号： F25B47/022 , F25C5/10
摘要： Disclosed is a refrigerant circuit for an ice making machine and the like, in which not only drop in the performance or damage of a compressor due to the abnormally elevated higher level pressure thereof but also double-freezing can effectively be prevented. The refrigerant circuit comprises a freezing circuit in which a vaporized refrigerant compressed in a compressor to high temperature and pressure levels is fed via a solenoid valve to a condenser, the refrigerant condensed in the condenser is then fed to an expansion means, the refrigerant vaporized through the expansion means is further fed to an evaporator, and the vaporized refrigerant heated through heat exchange with the evaporator is fed back to the compressor; and a hot gas circuit which bypasses the high-pressure and high-temperature vaporized refrigerant fed from the compressor to the evaporator via a hot gas valve so as to achieve ice releasing and the like at the evaporator; the solenoid valve and the hot gas valve being designed to be let open and closed, respectively, during the freezing operation and to be closed and let open, respectively, when the operation mode is switched to the ice releasing operation; wherein the solenoid valve is designed to be let open before completion of the ice releasing operation.
摘要翻译：公开了一种用于制冰机等的制冷剂回路，其中不仅可以有效地防止由于其异常升高的较高水平压力而且双重冻结而导致的压缩机性能下降或损坏。制冷剂回路包括冷冻回路，其中在压缩机中被压缩至高温和高压的汽化制冷剂通过电磁阀供给冷凝器，然后将在冷凝器中冷凝的制冷剂送入膨胀装置，制冷剂通过膨胀装置进一步供给到蒸发器，并且通过与蒸发器的热交换而加热的蒸发的制冷剂被反馈到压缩机; 以及热气回路，其绕过从压缩机经由热气阀向蒸发器供给的高压高温汽化制冷剂，以在蒸发器中实现冰的释放等; 电磁阀和热气阀被分别设计成在冷冻运行期间分开地关闭，并且当操作模式切换到冰释放操作时分别关闭和断开; 其中所述电磁阀被设计成在完成所述冰释放操作之前使其开启。

42. 发明授权

US5463504A Magnetic disk system and waveform equalizer therefor 失效
标题翻译：磁盘系统及其波形均衡器
公开(公告)号：US5463504A
公开(公告)日：1995-10-31
申请号：US62770
申请日：1993-05-18
申请人： Hiroshi Kimura , Shoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Akihiko Hirano , Akira Uragami
发明人： Hiroshi Kimura , Shoichi Miyazawa , Ryutaro Horita , Kenichi Hase , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/12 , G11B20/14
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/10222 , G11B20/1403 , G11B5/012 , G11B5/09 , G11B20/1258
摘要： A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled. Consequently, the delay characteristic is not affected by disparity of circuit components of the transversal circuit, and the write clock frequency and the delay time of the transversal circuit can be set to intended values by merely changing the value stored in the register in response to a variation of the data transfer rate.
摘要翻译：根据磁盘上的轨道位置以不同的数据传输速率记录和再现磁盘上的数据的磁盘系统包括对读出波形实现最佳波形整形的横向波形均衡电路。波形均衡电路由寄存器，频率合成器，PLL和横向电路组成。横向电路由可变延迟电路，可变增益放大器和加法器组成。频率合成器产生具有对应于存储在寄存器中的取决于数据传输速率的值的频率的写时钟信号，并且PLL响应于写时钟信号以产生控制信号，通过该控制信号，横向延迟时间电路被控制。因此，延迟特性不受横向电路的电路部件的不均匀影响，并且横向电路的写入时钟频率和延迟时间可以通过仅响应于一个变化来改变存储在寄存器中的值来设置为预期值数据传输速率的变化。

43. 发明授权

US5404250A Magnetic disk storage apparatus with phase sync circuit having controllable response characteristic 失效
标题翻译：具有可控响应特性的相位同步电路的磁盘存储装置
公开(公告)号：US5404250A
公开(公告)日：1995-04-04
申请号：US177694
申请日：1994-01-04
申请人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
发明人： Kenichi Hase , Syoichi Miyazawa , Ryutaro Horita , Shinichi Kojima , Akihiko Hirano , Akira Uragami
IPC分类号： G11B5/012 , G11B20/14 , H03K3/282 , H03L7/089 , H03L7/093 , H03L7/095 , H03L7/099 , H03L7/107 , H04L7/033 , G11B5/09 , H03K5/00 , H03L7/00
CPC分类号： H03L7/093 , G11B20/1403 , G11B5/012 , H03K3/2821 , H03L7/089 , H03L7/0895 , H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/107 , G11B2020/10916 , H03L2207/06 , H04L7/033
摘要： A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.
摘要翻译：磁盘存储装置提供锁相环或包括相位比较器，电荷泵，滤波器和压控振荡器的相位同步电路。相位同步电路包括连接到信息处理系统并适合于从信息处理系统指示的其中存储相位比较器，电荷泵，滤波器和压控振荡器的响应特性的寄存器。以这种方式，根据关于来自信息处理系统的响应特性的信息，控制相位同步电路，从而即使在内外轨道之间变化的数据传输速度的情况下也可以确保稳定的操作，例如发生在磁盘。

44. 发明授权

US4986083A Freezer machine 失效
标题翻译：冷冻机
公开(公告)号：US4986083A
公开(公告)日：1991-01-22
申请号：US487010
申请日：1990-03-01
申请人： Nobutaka Naruse , Akihiko Hirano , Katsunobu Minari
发明人： Nobutaka Naruse , Akihiko Hirano , Katsunobu Minari
IPC分类号： F25D11/00 , F25B1/00 , F25B47/02 , F25C1/00 , F25C5/10
CPC分类号： F25B47/022 , F25C5/10
摘要： In a freezer machine having a refrigeration system in the form of a circulation circuit including a compressor, a condenser, an evaporator coil arranged for thermal exchange with a freezing receptacle, and a solenoid valve of the normally closed type disposed within a bypass circuit of the circulation circuit to supply therethrough the hot gas outflowing from the compressor directly into the evaporator coil when it has been energized, an electric control circuit for the freezer machine is designed to repeatedly measure a first predetermined period of time, for instance four hours, in a condition where said compressor is being deactivated, to measure a second predetermined period of time, for instance three minutes, upon each lapse of the first predetermined period of time and to activate the compressor for the second predetermined period of time upon each lapse of the first predetermined period of time and energize the solenoid valve in response to activation of the compressor.
摘要翻译：在具有循环回路形式的制冷系统的冷冻机中，所述制冷系统包括压缩机，冷凝器，布置成与冷冻容器进行热交换的蒸发器盘管，以及设置在所述常闭型的旁路回路内的常闭型电磁阀循环回路供给从压缩机直接输出到蒸发器盘管中的热气体在通电时，用于冷冻机的电气控制回路被设计成在第一预定时间段（例如四小时）中反复测量在所述压缩机被停用的状态下，在每次经过所述第一预定时间段时测量第二预定时间段（例如三分钟），并且在每次经过所述第一预定时间段时将所述压缩机启动所述第二预定时间段响应于压缩机的启动而使电磁阀通电。

45. 发明申请

US20100269534A1 Ice making drum for drum type ice making machine 审中-公开
标题翻译：鼓式制冰机制冰鼓
公开(公告)号：US20100269534A1
公开(公告)日：2010-10-28
申请号：US12386801
申请日：2009-04-23
申请人： Yoshiaki Kumakiri , Atsushi Sugita , Akihiko Hirano
发明人： Yoshiaki Kumakiri , Atsushi Sugita , Akihiko Hirano
IPC分类号： F25C1/10
CPC分类号： F25B39/02 , F25C1/10
摘要： An ice making drum with an improved ice making performance includes a cylindrical drum body, rotational shafts, and shaft members respectively provided at the end faces of the drum body. The drum body has refrigerant flow passages which are each defined by an outer wall portion forming an outer surface, an internal wall portion set apart from the outer wall portion inwardly in a radial direction, and adjoining partition portions extending between the outer wall portion and the internal wall portion. The whole drum body is integrally formed of the same metallic material.
摘要翻译：具有改进的制冰性能的制冰滚筒包括分别设置在滚筒本体的端面处的圆柱形鼓体，旋转轴和轴构件。鼓体具有制冷剂流动通道，每个制冷剂流动通道由形成外表面的外壁部分，与外壁部分沿径向向内设置的内壁部分以及在外壁部分和外壁部分之间延伸的邻接的分隔部分内壁部分。整个鼓体由相同的金属材料整体形成。

46. 发明授权

US06697976B1 Performance evaluation method, performance evaluation system, and information storage apparatus using same 失效
标题翻译：绩效考核方法，绩效评价体系以及使用该评价体系的信息存储装置
公开(公告)号：US06697976B1
公开(公告)日：2004-02-24
申请号：US09597272
申请日：2000-06-19
申请人： Naoki Satoh , Yasuyuki Ito , Akihiko Hirano , Terumi Takashi , Mikio Suzuki
发明人： Naoki Satoh , Yasuyuki Ito , Akihiko Hirano , Terumi Takashi , Mikio Suzuki
IPC分类号： G06F1100
CPC分类号： G11B20/18 , G06F11/076
摘要： Data byte errors are detected by a comparator and classified into errors for respective interleaves, and the classified errors are counted by counters in an error count block. Further, at the time one sector has been read, comparators compare the counted values for the respective interleaves with an interleave threshold to detect whether nor not there are interleaves which have a number of errors exceeding the interleave threshold, and the detected results are counted by an error count block. The frequency of retries after an ECC is predicted from the counted value on the error count block and the total number of read sectors.
摘要翻译：数据字节错误由比较器检测并分类为相应交错的错误，分类错误由错误计数块中的计数器计数。此外，在读取一个扇区时，比较器将交织的计数值与交织阈值进行比较，以检测是否存在具有超过交织阈值的错误数量的交织，并且将检测结果计数为一个错误计数块。根据误差计数块上的计数值和读取扇区总数来预测ECC之后的重试次数。

47. 发明授权

US6104331A Reproduced signal processing method, reproduced signal processing circuit, and a magnetic storage apparatus 有权
标题翻译：再现信号处理方法，再现信号处理电路和磁存储装置
公开(公告)号：US6104331A
公开(公告)日：2000-08-15
申请号：US161734
申请日：1998-09-29
申请人： Yoshiteru Ishida , Naoki Satoh , Terumi Takashi , Akihiko Hirano , Seiichi Mita
发明人： Yoshiteru Ishida , Naoki Satoh , Terumi Takashi , Akihiko Hirano , Seiichi Mita
IPC分类号： G11B5/09 , G11B5/012 , G11B19/04 , G11B20/10 , G11B20/24 , G11B23/00 , H03M1/12 , G11B5/02
CPC分类号： G11B19/04 , G11B20/10009 , G11B20/24 , G11B5/012 , G11B23/0007 , G11B5/09
摘要： A reproduced signal processing circuit includes a variable gain amplifier to which a signal read from a medium by a reproducing head is inputted; an analog-to-digital converter for converting a signal outputted from the variable gain amplifier into a digital signal; and a variable frequency oscillator for supplying an operation clock signal to the analog-to-digital converter. A reproduced signal processing method includes the steps of operating a first control loop for controlling the variable gain amplifier; operating at least either one of a second control loop and a third control loop, the second control loop controlling the variable frequency oscillator, the third control loop controlling the variable frequency oscillator; filtering by analog filter means the read signal inputted to the variable gain amplifier; operating at least one of first, second, and third noise detecting operations, the first noise detecting operation detecting presence or absence of a noise by comparing an amplitude of the output signal from the variable gain amplifier with a predetermined threshold value, the second noise detecting operation detecting a noise during an operation period of the second control loop, the third noise detecting operation detecting a noise during an operation period of the third control loop; and changing the range of cutoff frequency of the analog filter means in accordance with a result from at least one of the first, second, and third noise detecting operations, thereby controlling at least one of the first, second, and third control loops.
摘要翻译：再现信号处理电路包括可变增益放大器，从再现头从介质读取的信号被输入到该可变增益放大器; 用于将从可变增益放大器输出的信号转换为数字信号的模拟 - 数字转换器; 以及用于向模数转换器提供操作时钟信号的可变频率振荡器。再现信号处理方法包括以下步骤：操作用于控制可变增益放大器的第一控制环路; 操作第二控制回路和第三控制回路中的至少一个，控制可变频率振荡器的第二控制回路，控制可变频率振荡器的第三控制回路; 通过模拟滤波器滤波意味着输入到可变增益放大器的读取信号; 操作第一，第二和第三噪声检测操作中的至少一个，所述第一噪声检测操作通过将来自可变增益放大器的输出信号的幅度与预定阈值进行比较来检测噪声的存在或不存在，第二噪声检测操作在第二控制回路的操作期间检测噪声，第三噪声检测操作在第三控制回路的操作期间检测噪声; 以及根据第一，第二和第三噪声检测操作中的至少一个的结果改变模拟滤波器装置的截止频率的范围，从而控制第一，第二和第三控制回路中的至少一个。

48. 发明授权

US5818655A Signal processing circuit and information recording/reproducing apparatus using the same, and method for optimizing coefficients of equalizer circuit 失效
公开(公告)号：US5818655A
公开(公告)日：1998-10-06
申请号：US506635
申请日：1995-07-25
申请人： Naoki Satoh , Seiichi Mita , Shoichi Miyazawa , Terumi Takashi , Yosuke Hori , Yoshiju Watanabe , Akihiko Hirano , Satoshi Minoshima , Hideki Miyasaka , Toshihiro Nitta , Tomoaki Hirai , Ryushi Shimokawa , Koji Shida , Yasuhide Ouchi
发明人： Naoki Satoh , Seiichi Mita , Shoichi Miyazawa , Terumi Takashi , Yosuke Hori , Yoshiju Watanabe , Akihiko Hirano , Satoshi Minoshima , Hideki Miyasaka , Toshihiro Nitta , Tomoaki Hirai , Ryushi Shimokawa , Koji Shida , Yasuhide Ouchi
IPC分类号： G11B5/035 , G11B5/09 , G11B20/10
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10481 , G11B5/035 , G11B5/09
摘要： A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

49. 发明授权

US5553104A Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal 失效
标题翻译：具有用于从输入数据信号中提取时钟信号的时钟定时提取电路的信息记录/再现装置
公开(公告)号：US5553104A
公开(公告)日：1996-09-03
申请号：US266779
申请日：1994-06-29
申请人： Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
发明人： Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
IPC分类号： G11B20/14 , G11B27/30 , H03L7/06 , H03L7/081 , H03L7/099 , H03L7/183 , H04L7/033 , H03D3/24
CPC分类号： H03L7/0996 , G11B20/1403 , G11B27/30 , H03L7/081 , H03L7/183 , H04L7/0337
摘要： A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.
摘要翻译：用于信息记录/再现装置的时钟定时提取电路具有一个相位比较器，用于将再生信号与所选择的时钟信号进行比较以产生相位误差信号;时钟信号产生电路，用于调整频率以使误差信号接近根据相位误差信号输出零，并输出具有相互不同的相位差的多个时钟信号，用于基于选择信号输出多个时钟信号中的一个的选择电路，用于确定其中之一的相位差判定电路具有最小相位误差（Vdet）的多个时钟信号，并且产生用于选择具有最小相位差的时钟信号的选择信号，以及用于阻止相位比较器的输出的冻结电路，直到具有最小相位误差的时钟信号被选中。信息记录/重放装置具有用于限制从记录介质接收的再现信号的幅度的AGC电路，上述时钟定时提取电路和解码器电路。时钟定时提取电路从AGC电路的输出信号中提取时钟信号，解码器根据所提取的时钟信号对AGC电路的输出信号进行解码。

50. 发明授权

US07444829B2 Automatic ice making machine 有权
标题翻译：自动制冰机
公开(公告)号：US07444829B2
公开(公告)日：2008-11-04
申请号：US10570582
申请日：2004-12-06
申请人： Kazuhiro Mori , Akihiko Hirano
发明人： Kazuhiro Mori , Akihiko Hirano
IPC分类号： F25C5/08
CPC分类号： F25C5/08 , F25C1/22
摘要： The peel off between an ice making plate and an insulating layer or between the insulating layer and heating means is prevented so that an ice making operation can be performed efficiently. Also, a metal plate is insulated from the heating means reliably.An evaporation pipe 14 and electric heaters H1 to HN are provided in an ice making member 11. A coolant is circulatingly supplied through the evaporation pipe 14 so as to cool the ice making member 11 and ice making water is supplied to the ice making member 11 so as to form an ice block M during the ice making operation. During the deicing operation, heat is generated in the heaters H1 to HN by applying current so that the ice block M is removed from the ice making member 11 by melting. The ice making member 11, in a state that an insulating layer 12b lies between a metal plate 12a to which the evaporation pipe 14 is fixed and the heaters H1 to HN, is formed by bonding the metal plate 12a with the insulating layer 12b, and the insulating layer 12b with each of the heaters H1 to HN by thermocompression. Also, in addition to thermocompression bonding, the external outline of the heating means (H1 to HN) may be located inside the insulating layer 12b.
摘要翻译：防止制冰板与绝缘层之间或绝缘层与加热装置之间的剥离，从而可以有效地进行制冰操作。此外，金属板与加热装置可靠地绝缘。蒸发管14和电加热器H 1至HN设置在制冰部件11中。通过蒸发管14循环地供给冷却剂，以便冷却制冰构件11，并且在制冰操作期间将制冰水供应到制冰构件11以形成冰块M. 在除冰操作期间，通过施加电流在加热器H 1至HN中产生热量，使得通过熔化将冰块M从制冰部件11移除。在绝热层12b位于固定有蒸发管14的金属板12a与加热器H 1〜HN之间的状态下，制冰部件11通过将金属板12a与绝缘体层12b和绝缘层12b，其中每个加热器H 1至HN通过热压。此外，除了热压接之外，加热装置（H 1至HN）的外部轮廓可以位于绝缘层12b内。

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