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1. 发明授权

US06483549B2 Video signal receiver with level limited output 失效
标题翻译：具有电平有限输出的视频信号接收器
公开(公告)号：US06483549B2
公开(公告)日：2002-11-19
申请号：US10040199
申请日：2001-10-23
申请人： Hideki Miyasaka , Hiroshi Ohtsuru , Tetsuya Yasui
发明人： Hideki Miyasaka , Hiroshi Ohtsuru , Tetsuya Yasui
IPC分类号： H04N514
CPC分类号： H04N5/21 , H04N5/20 , H04N9/646
摘要： A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
摘要翻译：视频信号处理装置包括接收输入视频信号并响应于此产生输出视频信号的接收机，设置输出视频信号的上限值和下限值中的至少一个的限制设置单元，以及限幅器提供来自接收器的输出视频信号，并且进一步具有来自限制设置单元的上限值和下限值中的至少一个，其中限幅器通过比较来限制由接收器产生的输出视频信号的电平根据任何上限值和下限值的输出视频信号的电平。

2. 发明授权

US06317163B1 Video signal receiver with level limited output 失效
标题翻译：具有电平有限输出的视频信号接收器
公开(公告)号：US06317163B1
公开(公告)日：2001-11-13
申请号：US09183372
申请日：1998-10-30
申请人： Hideki Miyasaka , Hiroshi Ohtsuru , Tetsuya Yasui
发明人： Hideki Miyasaka , Hiroshi Ohtsuru , Tetsuya Yasui
IPC分类号： H04N514
CPC分类号： H04N5/21 , H04N5/20 , H04N9/646
摘要： A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
摘要翻译：视频信号处理装置包括接收输入视频信号并响应于此产生输出视频信号的接收机，设置输出视频信号的上限值和下限值中的至少一个的限制设置单元，以及限幅器提供来自接收器的输出视频信号，并且进一步具有来自限制设置单元的上限值和下限值中的至少一个，其中限幅器通过比较来限制由接收器产生的输出视频信号的电平根据任何上限值和下限值的输出视频信号的电平。

3. 发明授权

US5752266A Method controlling memory access operations by changing respective priorities thereof, based on a situation of the memory, and a system and an integrated circuit implementing the method 失效
标题翻译：通过基于存储器的情况改变其优先级，以及实现该方法的系统和集成电路来控制存储器存取操作的方法
公开(公告)号：US5752266A
公开(公告)日：1998-05-12
申请号：US571493
申请日：1995-12-13
申请人： Katsuki Miyawaki , Yukio Otobe , Kimihiko Kazui , Hideki Miyasaka , Yasunori Ueno , Kouji Maruyama
发明人： Katsuki Miyawaki , Yukio Otobe , Kimihiko Kazui , Hideki Miyasaka , Yasunori Ueno , Kouji Maruyama
IPC分类号： G06F13/18 , G06F7/00
CPC分类号： G06F13/18
摘要： Control operations to access a memory changes respective priorities of the operations depending on the situation of the memory, and the operations are arbitrated and scheduled according to the respective, changed priorities, in order to avoid concentration on or rejection of a specific memory access operations and to eliminate an ineffective period. This realizes an efficient memory system without increasing the capacity of a buffer memory, the width of a memory bus, or an operating frequency.
摘要翻译：访问存储器的控制操作根据存储器的情况改变操作的各个优先级，并且根据各自的改变的优先级对操作进行仲裁和调度，以避免集中或拒绝特定存储器存取操作，消除无效期。这实现了高效的存储器系统，而不增加缓冲存储器的容量，存储器总线的宽度或工作频率。

4. 发明授权

US5572157A Digital phase-looked loop circuit 失效
标题翻译：数字相位环路电路
公开(公告)号：US5572157A
公开(公告)日：1996-11-05
申请号：US21854
申请日：1993-02-24
申请人： Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
发明人： Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
IPC分类号： H03K5/00 , H03L7/06 , H03L7/08 , H03L7/093 , H03L7/10 , H03L7/085
CPC分类号： H03L7/10 , H03L7/093
摘要： Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator 8 for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.
摘要翻译：来自计数器15的计数脉冲CTP通过双分频器17被提供给相位检测器3，以产生表示与同步峰值脉冲PK相位相差的测量数据N1。在减法器4中，为了减少稳态相位误差的数量，从寄存器13补偿测量数据N1的误差数据Ne。由减法器4产生的内部相位误差DELTA N被提供给在其数字滤波器7中进行补偿处理的LPF5。 LPF5还包括相位补偿器6和周期补偿器8，用于通过数字滤波器7中的内相位误差DELTA N补偿控制延迟体验。使用由LPF 5输出的计数器振荡周期数据OPD的整数部分OPD1 用于确定计数器15的振荡周期，而其分数部分OPD2通过加法器11积累在寄存器12中。寄存器12中累积的误差被传送到寄存器13并作为误差数据Ne存储。因此，采集时间缩短，稳态误差的数量也减少。

5. 发明授权

US5991503A Moving picture data storing system and moving picture data decoding system 失效
标题翻译：运动图像数据存储系统和运动图像数据解码系统
公开(公告)号：US5991503A
公开(公告)日：1999-11-23
申请号：US661023
申请日：1996-06-10
申请人： Hideki Miyasaka , Hideaki Watanabe , Takehira Masanori , Kiyoshi Maeda , Masao Mutou , Hirohiko Inagaki
发明人： Hideki Miyasaka , Hideaki Watanabe , Takehira Masanori , Kiyoshi Maeda , Masao Mutou , Hirohiko Inagaki
IPC分类号： H04N5/92 , H03M7/36 , H04N5/783 , H04N5/937 , H04N9/804 , H04N19/102 , H04N19/114 , H04N19/152 , H04N19/159 , H04N19/162 , H04N19/169 , H04N19/37 , H04N19/423 , H04N19/46 , H04N19/50 , H04N19/503 , H04N19/577 , H04N19/65 , H04N19/70 , H04N5/917 , H04N7/26
CPC分类号： H04N19/00 , H04N19/423 , H04N19/61 , H04N5/783 , H04N19/70 , H04N9/8042
摘要： An encoding unit encodes and compresses picture data in a bit map format corresponding to the MPEG method. A packet assembling portion assembles the picture data encoded by the encoding unit as packets in the format corresponding to the MPEG method, and stores the packets to a storing medium. At this point, the packet assembling portion writes an I picture index to a packet that contains at least a part of I picture data. When a special reproducing operation is performed, a data storing unit reads only packets that have the I picture index. A decoding unit decodes only I picture data of picture data contained in packets read from the storing medium and displays the decoded picture data.
摘要翻译：编码单元以与MPEG方法对应的位图格式对图像数据进行编码和压缩。分组组合部分将由编码单元编码的图像数据组合为与MPEG方法对应的格式的分组，并将分组存储到存储介质。在这一点上，分组组合部分将I图像索引写入包含I图像数据的至少一部分的分组。当执行特殊的再现操作时，数据存储单元仅读取具有I图像索引的数据包。解码单元仅解码从存储介质读取的分组中包含的图像数据的I图像数据，并显示解码的图像数据。

6. 发明授权

US5841303A Digital phase-locked loop circuit 失效
标题翻译：数字锁相环电路
公开(公告)号：US5841303A
公开(公告)日：1998-11-24
申请号：US742678
申请日：1996-10-31
申请人： Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
发明人： Terumi Takashi , Kazunori Iwabuchi , Minoru Kosuge , Hiromi Matsushige , Hideki Miyasaka
IPC分类号： H03K5/00 , H03L7/06 , H03L7/08 , H03L7/093 , H03L7/10 , H03L7/085
CPC分类号： H03L7/10 , H03L7/093
摘要： Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.
摘要翻译：来自计数器15的计数脉冲CTP通过双分频器17被提供给相位检测器3，以产生表示与同步峰值脉冲PK相位相差的测量数据N1。在减法器4中，为了减少稳态相位误差的数量，从寄存器13补偿测量数据N1的误差数据Ne。由减法器4产生的内部相位误差DELTA N被提供给在其数字滤波器7中进行补偿处理的LPF 5。 LPF5还包括相位补偿器6和周期补偿器，用于通过数字滤波器7中的内部相位误差DELTA N来补偿控制延迟体验。由LPF 5输出的计数器振荡周期数据OPD的整数部分OPD1用于确定计数器15的振荡周期，而其分数部分OPD2通过加法器11积累在寄存器12中。寄存器12中累积的误差被传送到寄存器13并存储在其中作为误差数据Ne。因此，采集时间缩短，稳态误差的数量也减少。

7. 发明授权

US06661594B2 Signal processing circuit and information recording/reproducing apparatus using the same, and method for optimizing coefficients of equalizer circuit 有权
标题翻译：信号处理电路和使用该信号的信息记录/再现装置，以及用于优化均衡器电路的系数的方法
公开(公告)号：US06661594B2
公开(公告)日：2003-12-09
申请号：US10277695
申请日：2002-10-23
申请人： Naoki Satoh , Seiichi Mita , Shoichi Miyazawa , Terumi Takashi , Yosuke Hori , Yoshiju Watanabe , Akihiko Hirano , Satoshi Minoshima , Hideki Miyasaka , Toshihiro Nitta , Tomoaki Hirai , Ryushi Shimokawa , Koji Shida , Yasuhide Ouchi
发明人： Naoki Satoh , Seiichi Mita , Shoichi Miyazawa , Terumi Takashi , Yosuke Hori , Yoshiju Watanabe , Akihiko Hirano , Satoshi Minoshima , Hideki Miyasaka , Toshihiro Nitta , Tomoaki Hirai , Ryushi Shimokawa , Koji Shida , Yasuhide Ouchi
IPC分类号： G11B535
CPC分类号： G11B20/10055 , G11B5/035 , G11B5/09 , G11B20/10009 , G11B20/10481
摘要： A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.
摘要翻译：一种用于至少包括AGC，PLL，LPF，均衡器电路和检测电路的磁记录/再现装置的信号处理电路，其中通过定义均衡器电路的结构形成系数补偿电路，错误提供检测电路，其通过接收来自检测电路的输入而工作，并且LSI由多个模拟和数字芯片形成，并且模拟和数字芯片通过电流输出型D / A转换器连接至少至少 AGC和PLL。

8. 发明授权

US5177797A Block transformation coding and decoding system with offset block division 失效
标题翻译：具有偏移块分段的块变换编码和解码系统
公开(公告)号：US5177797A
公开(公告)日：1993-01-05
申请号：US496006
申请日：1990-03-20
申请人： Yuji Takenaka , Yoshitsugu Nishizawa , Takahiro Hosokawa , Yuji Mori , Hideki Miyasaka
发明人： Yuji Takenaka , Yoshitsugu Nishizawa , Takahiro Hosokawa , Yuji Mori , Hideki Miyasaka
IPC分类号： H04N1/19 , G06T9/00 , H04N1/40 , H04N1/41 , H04N1/415
CPC分类号： H04N19/60 , H04N19/30
摘要： An image data coding system, wherein an image data in a bit map form is divided into first and second groups, pixels in each group of which are distributed over the whole area of the image data in the bit map form. First and second coders respectively code the first and second groups of image data into first and second groups of coded image data. The first and second groups of image data in the original image data are respectively input into first and second memories, respectively. Blocks of the first group of image data are supplied to the first coder at first times, respectively, and blocks of the second group of image data are supplied to the second coder at second times, respectively. Boundaries of the blocks in the first group of image data are located in different positions from boundaries of the blocks in the second group of image data, and the first times are different from the second times. In the receiver side, first and second decoders respectively decode the above first and second groups of coded image data into first and second groups of decoded image data. By composing the first and second groups of decoded image data, the original image data in the bit map form is restored.
摘要翻译：一种图像数据编码系统，其中位图形式的图像数据被划分为第一组和第二组，每组中的像素以位图形式分布在图像数据的整个区域上。第一和第二编码器分别将第一和第二组图像数据编码为第一组和第二组编码图像数据。分别将原始图像数据中的第一组图像数据和第二组图像数据分别输入到第一和第二存储器中。第一组图像数据的块分别在第一次被提供给第一编码器，并且第二组图像数据的块分别在第二次被提供给第二编码器。第一组图像数据中的块的边界位于与第二组图像数据中的块的边界不同的位置，并且第一次与第二次不同。在接收机侧，第一和第二解码器分别将上述第一组和第二组编码图像数据解码为第一组和第二组解码图像数据。通过构成第一组和第二组解码图像数据，恢复位图形式中的原始图像数据。

9. 发明授权

US06490004B2 Video signal receiver with level limited output 失效
公开(公告)号：US06490004B2
公开(公告)日：2002-12-03
申请号：US10040200
申请日：2001-10-23
申请人： Hideki Miyasaka , Hiroshi Ohtsuru , Tetsuya Yasui
发明人： Hideki Miyasaka , Hiroshi Ohtsuru , Tetsuya Yasui
IPC分类号： H04N514
CPC分类号： H04N5/21 , H04N5/20 , H04N9/646
摘要： A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

10. 发明授权

US06490003B2 Video signal receiver with level limited output 失效
公开(公告)号：US06490003B2
公开(公告)日：2002-12-03
申请号：US10040198
申请日：2001-10-23
申请人： Hideki Miyasaka , Hiroshi Ohtsuru , Tetsuya Yasui
发明人： Hideki Miyasaka , Hiroshi Ohtsuru , Tetsuya Yasui
IPC分类号： H04N514
CPC分类号： H04N5/21 , H04N5/20 , H04N9/646
摘要： A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.

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