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1. 发明授权

US5553104A Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal 失效
标题翻译：具有用于从输入数据信号中提取时钟信号的时钟定时提取电路的信息记录/再现装置
公开(公告)号：US5553104A
公开(公告)日：1996-09-03
申请号：US266779
申请日：1994-06-29
申请人： Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
发明人： Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
IPC分类号： G11B20/14 , G11B27/30 , H03L7/06 , H03L7/081 , H03L7/099 , H03L7/183 , H04L7/033 , H03D3/24
CPC分类号： H03L7/0996 , G11B20/1403 , G11B27/30 , H03L7/081 , H03L7/183 , H04L7/0337
摘要： A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.
摘要翻译：用于信息记录/再现装置的时钟定时提取电路具有一个相位比较器，用于将再生信号与所选择的时钟信号进行比较以产生相位误差信号;时钟信号产生电路，用于调整频率以使误差信号接近根据相位误差信号输出零，并输出具有相互不同的相位差的多个时钟信号，用于基于选择信号输出多个时钟信号中的一个的选择电路，用于确定其中之一的相位差判定电路具有最小相位误差（Vdet）的多个时钟信号，并且产生用于选择具有最小相位差的时钟信号的选择信号，以及用于阻止相位比较器的输出的冻结电路，直到具有最小相位误差的时钟信号被选中。信息记录/重放装置具有用于限制从记录介质接收的再现信号的幅度的AGC电路，上述时钟定时提取电路和解码器电路。时钟定时提取电路从AGC电路的输出信号中提取时钟信号，解码器根据所提取的时钟信号对AGC电路的输出信号进行解码。

2. 发明授权

US5448424A AGC circuit and recording and reproducing apparatus using AGC circuit 失效
标题翻译： AGC电路和使用AGC电路的记录和再现设备
公开(公告)号：US5448424A
公开(公告)日：1995-09-05
申请号：US196478
申请日：1994-02-15
申请人： Akihiko Hirano , Terumi Takashi , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Minoru Kosuge
发明人： Akihiko Hirano , Terumi Takashi , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Minoru Kosuge
IPC分类号： G11B5/09 , G11B20/04 , G11B20/10 , G11B20/12 , G11B20/14 , H03G3/00 , H03G3/20 , H03G3/30 , H03G11/00 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1403 , H03G3/001 , G11B20/1252
摘要： An AGC circuit is provided with a variable gain amplifier which changes an amplification gain of an input signal in accordance with an instruction; an extraction unit for extracting a value of an output of the variable gain amplifier at a predetermined interval; and a variable gain control unit for instructing the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the value extracted by the extraction unit. The variable gain control unit is provided with an error signal output device for squaring the value extracted by the extraction unit and for generating an error signal to instruct the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the square value and a square value just before it; and an integrating device for integrating the error signal from the error signal output device and for instructing the amplification gain of the variable gain amplifier.
摘要翻译： AGC电路设置有根据指令改变输入信号的放大增益的可变增益放大器; 提取单元，用于以预定间隔提取可变增益放大器的输出值; 以及可变增益控制单元，用于以使得输入信号的幅度基于由提取单元提取的值等于预定幅度的方式来指示可变增益放大器的放大增益。可变增益控制单元设置有误差信号输出装置，用于对由提取单元提取的值进行平方，并产生误差信号，以使得输入信号的振幅为基于正方形值等于预定幅度和刚好在其前的平方值; 以及用于积分来自误差信号输出装置的误差信号并用于指示可变增益放大器的放大增益的积分装置。

3. 发明授权

US5625632A Magnetic disk drive including a data discrimination apparatus capable of correcting signal waveform distortion due to intersymbol interference 失效
标题翻译：磁盘驱动器包括能够校正由于符号间干扰引起的信号波形失真的数据鉴别装置
公开(公告)号：US5625632A
公开(公告)日：1997-04-29
申请号：US319725
申请日：1994-10-07
申请人： Yoshiteru Ishida , Kazunori Iwabuchi , Hideyuki Yamakawa , Hiromi Matsushige
发明人： Yoshiteru Ishida , Kazunori Iwabuchi , Hideyuki Yamakawa , Hiromi Matsushige
IPC分类号： G11B20/10 , G06F11/10 , H03M13/00
CPC分类号： G11B20/10009
摘要： A data discrimination apparatus which is capable of correcting a decrease in amplitude of a signal to be data discriminated by a correction value so as to correct the bit itself which was used as a target bit to determine the correction value. A decision circuit preliminarily classifies an equalizer output into symbols "0" and "1" to obtain a run length of the symbol "0" with respect to a given symbol "1" (the target bit). A correction value generating circuit includes a memory device which contains correction values in correspondence with all the possible values of the run length, and outputs one of the correction values out of the memory device in response to an output from the decision circuit. A delay circuit delays the equalizer output by a time which is required until the correction value is output. An operation circuit adds the selected correction value to the delayed equalizer output, to correct the same. The thus corrected equalizer output is data discriminated in a data discrimination circuit, with a lowered error rate owing to the correction.
摘要翻译：一种数据识别装置，其能够校正由校正值识别的要被数据的信号的幅度的降低，以便校正用作目标位的位本身以确定校正值。判定电路预先将均衡器输出分类为符号“0”和“1”，以获得相对于给定符号“1”（目标位）的符号“0”的游程长度。校正值产生电路包括存储器件，其存储与游程长度的所有可能值相对应的校正值，并且响应于来自判定电路的输出将一个校正值输出存储器件。延迟电路使均衡器输出延迟所需的时间，直到校正值被输出。操作电路将所选择的校正值与延迟均衡器输出相加，以校正相同的值。这样校正的均衡器输出是在数据鉴别电路中鉴别的数据，由于校正而导致的误差率降低。

4. 发明申请

US20050041316A1 Apparatus for information recording and reproducing 失效
公开(公告)号：US20050041316A1
公开(公告)日：2005-02-24
申请号：US10914243
申请日：2004-08-10
申请人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
发明人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/14 , G11B20/20
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09 , G11B20/1403
摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

5. 发明授权

US5844741A System for reproducing high-density magnetic record data with viterbi detector for generating quadripartite reproduction data 失效
标题翻译：用于产生四方再生数据的维特比检测器再现高密度磁记录数据的系统
公开(公告)号：US5844741A
公开(公告)日：1998-12-01
申请号：US548956
申请日：1995-10-27
申请人： Hideyuki Yamakawa , Takushi Nishiya , Takashi Nara , Terumi Takashi
发明人： Hideyuki Yamakawa , Takushi Nishiya , Takashi Nara , Terumi Takashi
IPC分类号： G11B20/14 , G11B5/012 , G11B5/09 , G11B20/10 , G11B20/18 , H03M13/23 , H04L25/08 , H04L25/497 , G11B5/035
CPC分类号： G11B20/10175 , G11B20/10009 , G11B5/012 , G11B5/09
摘要： A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.
摘要翻译：作为简单的结构，提供了以高密度再现记录在磁记录介质上的数据的系统。四维重放数据从维特比检测电路输出到加法器，然后从PR4-ML方法数据确定之前的信号中减去四方再生数据。使用加法器对结果执行（1 + D）处理。误差信号图案检测电路对PR4-ML方法检测误差进行最大似然估计。此外，当检测到的确定错误与实际再现数据串匹配时，数据校正电路校正再现数据串。

6. 发明授权

US06980385B2 Apparatus for information recording and reproducing 失效
标题翻译：用于信息记录和再现的装置
公开(公告)号：US06980385B2
公开(公告)日：2005-12-27
申请号：US10914243
申请日：2004-08-10
申请人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
发明人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
IPC分类号： G11B5/012 , G11B5/09 , G11B20/10 , G11B20/14
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09 , G11B20/1403
摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
摘要翻译：为了产生具有更高精度的采样时钟，同步信号发生电路设置有相位误差检测器，检测基于FDTS算法数字化的读出信号的相位误差和控制振荡频率的VCO 基于由相位误差检测器检测到的相位误差，由VCO产生同步信号。基于由同步信号发生电路产生的同步信号，ADC对读出的信号进行数字化。然后，数字化读出信号由检测电路转换成二进制数据。

7. 发明授权

US06791776B2 Apparatus for information recording and reproducing 失效
标题翻译：用于信息记录和再现的装置
公开(公告)号：US06791776B2
公开(公告)日：2004-09-14
申请号：US09793924
申请日：2001-02-28
申请人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
发明人： Takatoshi Kato , Takushi Nishiya , Hideyuki Yamakawa , Takashi Nara , Nobuaki Nakai , Hiroshi Ide , Shintaro Suzumura , Terumi Takashi
IPC分类号： G11B509
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09 , G11B20/1403
摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.
摘要翻译：为了产生具有更高精度的采样时钟，同步信号发生电路设置有相位误差检测器，检测基于FDTS算法数字化的读出信号的相位误差和控制振荡频率的VCO 基于由相位误差检测器检测到的相位误差，由VCO产生同步信号。基于由同步信号发生电路产生的同步信号，ADC对读出的信号进行数字化。然后，数字化读出信号由检测电路转换成二进制数据。

8. 发明授权

US5940416A Digital signal decoding apparatus and a decoding method used therein 失效
标题翻译：数字信号解码装置及其中使用的解码方法
公开(公告)号：US5940416A
公开(公告)日：1999-08-17
申请号：US881508
申请日：1997-06-24
申请人： Takushi Nishiya , Hideyuki Yamakawa , Shoichi Miyazawa, deceased , Seiichi Mita , Yoichi Uehara , Takashi Nara , Akihiko Hirano
发明人： Takushi Nishiya , Hideyuki Yamakawa , Shoichi Miyazawa, deceased , Seiichi Mita , Yoichi Uehara , Takashi Nara , Akihiko Hirano
IPC分类号： G11B20/18 , G11B20/10 , H03M13/23 , H03M13/41 , H04L25/497 , H03M13/00
CPC分类号： H03M13/6505 , G11B20/10009 , H03M13/3961 , H03M13/4107
摘要： A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.
摘要翻译：关于信号输入的计算从扩展部分响应类的格状图上的分支度量计算处理中去除，并且分支度量的计算和幸存路径的选择可以通过减去幸存路径来执行和常数的比较。

9. 发明授权

US07370266B2 Digital signal decoding device and digital signal decoding method 失效
标题翻译：数字信号解码装置和数字信号解码方法
公开(公告)号：US07370266B2
公开(公告)日：2008-05-06
申请号：US10740531
申请日：2003-12-22
申请人： Hideyuki Yamakawa
发明人： Hideyuki Yamakawa
IPC分类号： H03M13/03
CPC分类号： G11B20/10046 , G11B20/10009 , G11B20/18 , G11B2020/1863 , H03M13/3961 , H03M13/4107 , H03M13/6343 , H03M13/6502
摘要： A digital signal decoding device according to an aspect of the present invention is a digital signal decoding device for generating a binary code sequence by maximum likelihood estimation from a convolutionally encoded input signal sequence, includes an add-compare-select unit configured to compare only two metric values one unit time before the calculation time of a predetermined branch metric value calculated from the input signal sequence at two successive times at each time, to add the predetermined branch metric value to the two metric values independently of the compare process, to select one of the two sums in accordance with the comparison result of the two metric values, and to output the selected value as a metric value to be used at the next time.
摘要翻译：根据本发明的一个方面的数字信号解码装置是一种数字信号解码装置，用于通过卷积编码的输入信号序列的最大似然估计来产生二进制码序列，包括一个加法比较选择单元，度量值在从每个输入信号序列在每次连续两次计算的预定分支度量值的计算时间之前一个单位时间，以将独立于比较过程的预定分支度量值加到两个度量值中，以选择一个根据两个度量值的比较结果，将两个和值输出，并将所选择的值输出作为下次使用的度量值。

10. 发明申请

US20080019249A1 APPARATUS FOR REPRODUCING DATA ON RECORDING MEDIUM AND METHOD FOR REPRODUCING DATA ON THE MEDIUM 审中-公开
标题翻译：用于在记录介质上再现数据的装置和用于在介质上再现数据的方法
公开(公告)号：US20080019249A1
公开(公告)日：2008-01-24
申请号：US11771906
申请日：2007-06-29
申请人： Yukiyasu Tatsuzawa , Hideyuki Yamakawa , Koichi Otake , Norikatsu Chiba , Yasuhiro Kanishima , Toshifumi Yamamoto , Toshihiko Kaneshige
发明人： Yukiyasu Tatsuzawa , Hideyuki Yamakawa , Koichi Otake , Norikatsu Chiba , Yasuhiro Kanishima , Toshifumi Yamamoto , Toshihiko Kaneshige
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10212 , G11B20/10296
摘要： An apparatus for reproducing digital data recorded on a recording medium by a Partial Response Maximum Likelihood method, the digital data being recorded in a code pattern in which the same code continuously appears at least two times, includes an analog-to-digital converting unit that samples an analog reproduction signal recorded on the recording medium and converts the sampled analog reproduction signal into a digital signal; a sampling rate switching unit that adaptively switches the sampling rate in the analog-to-digital converting unit from a higher rate to a lower rate; and a data demodulating unit that reproduces and demodulates the digital signal subjected to the analog-to-digital conversion in the analog-to-digital converting unit by the Partial Response Maximum Likelihood method in accordance with the switching between the higher rate and the lower rate.
摘要翻译：一种用于通过部分响应最大似然方法再现记录在记录介质上的数字数据的装置，所述数字数据以相同代码连续出现至少两次的代码模式被记录，包括模数转换单元，模数转换单元采样记录在记录介质上的模拟再现信号，并将采样的模拟再现信号转换为数字信号; 采样率切换单元，其自适应地将模数转换单元中的采样率从较高速率切换到较低速率; 以及数据解调单元，其通过部分响应最大似然方法根据较高速率和较低速率之间的切换再现和解调在模数转换单元中经受模数转换的数字信号。

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