专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20140218999A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20140218999A1
公开(公告)日：2014-08-07
申请号：US14124725
申请日：2011-06-10
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Akira Kotabe , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Akira Kotabe , Takashi Kobayashi
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/71 , G11C2213/75 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
摘要翻译：为了提供适合于小型化并允许接触电阻降低的半导体存储器件，存储器阵列（MA）的布线结构如下形成。也就是说，字线（2）和位线（3）彼此并行扩展，每条字线与另一个字线捆绑，每个位线与另一个位线捆绑，并且两个位线在相应的捆绑的两条字线上垂直形成的电路分离。这样的配置使得可以：在电线的捆扎部分（MLC）处形成更大的接触; 并降低适于小型化的存储器阵列中的接触电阻。

42. 发明授权

US08592789B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
公开(公告)号：US08592789B2
公开(公告)日：2013-11-26
申请号：US13109985
申请日：2011-05-17
申请人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Takashi Kobayashi
发明人： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Takashi Kobayashi
IPC分类号： H01L45/00
CPC分类号： H01L27/2481 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L27/2472
摘要： In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.

43. 发明申请

US20130075684A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20130075684A1
公开(公告)日：2013-03-28
申请号：US13588112
申请日：2012-08-17
申请人： Masaharu Kinoshita , Yoshitaka Sasago , Takashi Kobayashi , Hiroyuki Minemura
发明人： Masaharu Kinoshita , Yoshitaka Sasago , Takashi Kobayashi , Hiroyuki Minemura
IPC分类号： H01L45/00 , B82Y99/00
CPC分类号： H01L45/144 , G11C13/0004 , G11C2213/71 , G11C2213/74 , G11C2213/75 , G11C2213/78 , H01L27/2409 , H01L27/2481 , H01L45/06
摘要： A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.
摘要翻译：非易失性存储器件包括：沿衬底的主表面延伸的第一线; 提供在第一行之上的堆栈; 在堆叠之上形成第二线; 设置在所述第一和第二线相交的选择元件，所述选择元件适于在垂直于所述主表面的方向上传递电流; 沿着所述堆叠的侧表面设置的第二绝缘膜; 沿所述第二绝缘膜设置的沟道层; 沿着沟道层提供的粘合层; 以及沿着粘合层设置的可变电阻材料层，其中第一和第二线经由选择元件和沟道层电连接，通过沟道层和可变电阻材料层之间的粘合层的接触电阻低，并且粘合层的电阻相对于沟道层的延伸方向高。

44. 发明授权

US08735865B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08735865B2
公开(公告)日：2014-05-27
申请号：US12987109
申请日：2011-01-08
申请人： Hiroyuki Minemura , Yumiko Anzai , Takahiro Morikawa , Toshimichi Shintani , Yoshitaka Sasago
发明人： Hiroyuki Minemura , Yumiko Anzai , Takahiro Morikawa , Toshimichi Shintani , Yoshitaka Sasago
IPC分类号： H01L29/02 , H01L29/06 , G11C11/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/71 , G11C2213/75 , H01L27/2409 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/1286 , H01L45/1293 , H01L45/144
摘要： For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing.
摘要翻译：为了同时降低记录电流和抑制交叉擦除，提供了一种用于通过提供硫族化物型界面层来获得更高灵敏度和更高可靠性的三维相变存储器，其中电阻率，热导率和适当地选择界面层的材料的熔点，从而提高相变材料的电流浓度和写入时Si通道的热和材料绝缘性能。

45. 发明申请

US20110235408A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110235408A1
公开(公告)日：2011-09-29
申请号：US12987109
申请日：2011-01-08
申请人： Hiroyuki MINEMURA , Yumiko Anzai , Takahiro Morikawa , Toshimichi Shintani , Yoshitaka Sasago
发明人： Hiroyuki MINEMURA , Yumiko Anzai , Takahiro Morikawa , Toshimichi Shintani , Yoshitaka Sasago
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： H01L27/2481 , G11C13/0004 , G11C13/0069 , G11C2013/008 , G11C2213/71 , G11C2213/75 , H01L27/2409 , H01L27/2454 , H01L45/06 , H01L45/1233 , H01L45/1286 , H01L45/1293 , H01L45/144
摘要： For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing.
摘要翻译：为了同时降低记录电流和抑制交叉擦除，提供了一种用于通过提供硫族化物型界面层来获得更高灵敏度和更高可靠性的三维相变存储器，其中电阻率，热导率和适当地选择界面层的材料的熔点，从而提高相变材料的电流浓度和写入时Si通道的热和材料绝缘性能。

46. 发明授权

US09391268B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09391268B2
公开(公告)日：2016-07-12
申请号：US14405721
申请日：2012-06-04
申请人： Yoshitaka Sasago
发明人： Yoshitaka Sasago
IPC分类号： H01L27/24 , H01L45/00 , G11C13/00
CPC分类号： H01L45/06 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2454 , H01L27/2481 , H01L45/122 , H01L45/1233 , H01L45/144
摘要： The purpose of the present invention is to provide a semiconductor storage device, which has small resistance in the ON state, and a small leak current in the OFF state, and which has a small-sized select transistor used therein. In this semiconductor storage device, a channel of a first select transistor that selects a memory cell array is electrically connected to each of the adjacent memory cell arrays (see FIG. 1).
摘要翻译：本发明的目的是提供一种半导体存储装置，其在导通状态下具有小的电阻，并且在关闭状态下具有小的漏电流，并且其中使用小型选择晶体管。在该半导体存储装置中，选择存储单元阵列的第一选择晶体管的沟道电连接到各相邻的存储单元阵列（参照图1）。

47. 发明授权

US07411242B2 Miniaturized virtual grounding nonvolatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：小型虚拟接地非易失性半导体存储器件及其制造方法
公开(公告)号：US07411242B2
公开(公告)日：2008-08-12
申请号：US11239338
申请日：2005-09-30
申请人： Takashi Kobayashi , Yoshitaka Sasago , Tsuyoshi Arigane , Yoshihiro Ikeda , Kenji Kanamitsu
发明人： Takashi Kobayashi , Yoshitaka Sasago , Tsuyoshi Arigane , Yoshihiro Ikeda , Kenji Kanamitsu
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11546 , H01L29/42324
摘要： The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.
摘要翻译：本发明的目的是提供一种新的非易失性半导体存储器件及其制造方法，其目的是使三层多晶硅栅极的虚拟接地型存储单元小型化，提高性能，提高产量。在根据本发明的存储器单元中，垂直于字线和沟道的浮动栅极的两个端面部分地通过电介质膜放置在第三栅极的顶部上。本发明可以减少非易失性半导体存储器件的存储单元面积，提高工作速度，提高产量。

48. 发明申请

US20070109870A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20070109870A1
公开(公告)日：2007-05-17
申请号：US11652023
申请日：2007-01-11
申请人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
发明人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
摘要翻译：在闪速存储器中需要抑制泄漏电流，因为随着存储器单元尺寸的减小，通道长度变短。在具有辅助电极的AND型存储器阵列中，虽然通过使用MOS晶体管的场隔离来减小存储单元面积，但是由于存储单元尺寸的减小，沟道方向的泄漏电流变大，导致出现像编程特性恶化，电流消耗增加，读取失败。为了实现该目的，在本发明中，通过在编程和读取操作期间将辅助电极并联布置的至少一个辅助电极作为负电压进行电隔离，并且通过使半导体衬底表面在上述辅助电极不导电。

49. 发明授权

US07190017B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07190017B2
公开(公告)日：2007-03-13
申请号：US11022773
申请日：2004-12-28
申请人： Yoshitaka Sasago , Takashi Kobayashi
发明人： Yoshitaka Sasago , Takashi Kobayashi
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L27/11531
摘要： Reliability of a semiconductor device having a nonvolatile memory comprising first through third gate electrodes is enhanced. With a flash memory having first gate electrodes (floating gate electrodes), second gate electrodes (control gate electrodes) and third gate electrodes, isolation parts are formed in a self-aligned manner against patterns of a conductor film for forming the third gate electrodes by filling up the respective isolation grooves and a gate insulator film for select nMISes in a peripheral circuit region is formed prior to the formation of the isolation parts. By so doing, deficiency with the gate insulator film for the select nMISes, caused by stress occurring to the isolation parts, can be reduced. Further, with the semiconductor device including the case of stacked memory cells, the patterns of the conductor film for forming the third gate electrodes, serving as a mask for forming the isolation parts in the self-aligned manner, can be formed without misalignment against channels.
摘要翻译：具有包括第一至第三栅电极的非易失性存储器的半导体器件的可靠性得到增强。利用具有第一栅电极（浮栅电极），第二栅电极（控制栅电极）和第三栅电极的闪速存储器，隔离部分以自对准的方式形成，以抵抗用于形成第三栅电极的导体膜的图案填充相应的隔离沟槽，并且在形成隔离部件之前形成用于在外围电路区域中选择的nMIS的栅极绝缘膜。通过这样做，可以减少由隔离部分发生的应力引起的用于选择性nMIS的栅极绝缘膜的缺陷。此外，通过包括堆叠的存储单元的情况的半导体器件，可以形成用作形成隔离部件的自对准方式的掩模的用于形成第三栅电极的导体膜的图案，而不对准通道。

50. 发明授权

US07184318B2 Semiconductor memory device 有权
公开(公告)号：US07184318B2
公开(公告)日：2007-02-27
申请号：US11197485
申请日：2005-08-05
申请人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
发明人： Hideaki Kurata , Kazuo Otsuga , Yoshitaka Sasago , Takashi Kobayashi , Tsuyoshi Arigane
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0433 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L27/11524
摘要： Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式