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41. 发明授权

US07326621B2 Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate 有权
标题翻译：使用相对于硅衬底具有高蚀刻选择性的掩模层来制造凹槽通道阵列晶体管的方法
公开(公告)号：US07326621B2
公开(公告)日：2008-02-05
申请号：US11015366
申请日：2004-12-16
申请人： Young-sun Cho , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Ji-hong Kim , Hong-Mi Park
发明人： Young-sun Cho , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Ji-hong Kim , Hong-Mi Park
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/28061 , H01L21/28114 , H01L21/823487 , H01L29/42376
摘要： A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.
摘要翻译：一种制造凹槽通道阵列晶体管的方法。使用相对于硅衬底具有高蚀刻选择性的掩模层图案，蚀刻硅衬底和隔离绝缘层以形成凹槽沟道沟槽。在凹槽沟道沟槽上形成栅极绝缘层和凹槽叠层之后，在与硅栅极叠层的两个侧壁相邻的硅衬底中形成源极和漏极，由此完成凹槽沟道阵列晶体管。由于使用具有相对于硅衬底的高蚀刻选择性的掩模层图案，所以可以容易地控制凹槽沟槽的深度，同时获得硅衬底的良好蚀刻均匀性。

42. 发明申请

US20070234538A1 Plurality of capacitors employing holding layer patterns and method of fabricating the same 审中-公开
标题翻译：采用保持层图案的多种电容器及其制造方法
公开(公告)号：US20070234538A1
公开(公告)日：2007-10-11
申请号：US11727123
申请日：2007-03-23
申请人： Tae-Hyuk Ahn
发明人： Tae-Hyuk Ahn
IPC分类号： H05K3/00 , H04R17/00
CPC分类号： H01L28/91 , H01L27/0207 , H01L27/10814 , H01L27/10852 , Y10T29/42 , Y10T29/435 , Y10T29/49117 , Y10T29/49124
摘要： A plurality of capacitors employing holding layer patterns, and a method of fabricating the same, the plurality of capacitors including a plurality of cylinder-shaped lower plates repeatedly aligned in two dimensions. Holding layer patterns are located between the uppermost portions and the lowermost portions of the plurality of lower plates, and connect the adjacent side walls of the plurality of lower plates. An upper plate fills the spaces inside the plurality of lower plates and the spaces between the side walls of the plurality of lower plates. A capacitor dielectric layer is interposed between the plurality of lower plates and the upper plate, and insulates the lower plates and the upper plate.
摘要翻译：使用保持层图案的多个电容器及其制造方法，所述多个电容器包括在二维上重复排列的多个圆筒形下板。保持层图案位于多个下板的最上部和最下部之间，并且连接多个下板的相邻侧壁。上板填充多个下板中的空间和多个下板的侧壁之间的空间。在多个下板和上板之间插入电容器电介质层，并使下板和上板绝缘。

43. 发明申请

US20060222966A1 Mask layout and method of forming contact pad using the same 失效
标题翻译：使用其形成接触垫的掩模布局和方法
公开(公告)号：US20060222966A1
公开(公告)日：2006-10-05
申请号：US11342560
申请日：2006-01-31
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： H01L21/31144 , G03F1/00 , H01L21/76897
摘要： Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.
摘要翻译：提供了使用这种光掩模的接触光掩模和方法来制造半导体器件，并在暴露在栅极线之间的有源区域的部分上形成接触插塞。细长的有源区域被排列成一系列平行的组，每个组又沿它们的纵向轴线对准，以与栅极线形成锐角。接触光掩模包括以平行线布置的多个开口，其以与先前形成的栅极线偏移的角度排列，并且可以平行于有源区域，或者可以与两个活动组的轴线偏移的角度对准区域和栅极线。使用这种光掩模形成接触塞的方法可以提供增加的加工余量，并且扩展了展示增加的集成密度和/或构建到更苛刻的设计规则的半导体器件的常规曝光设备的效用。

44. 发明申请

US20050079673A1 Method of manufacturing a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US20050079673A1
公开(公告)日：2005-04-14
申请号：US10954835
申请日：2004-09-29
申请人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
发明人： Jung-woo Seo , Tae-hyuk Ahn , Jeong-sic Jeon
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76895 , H01L21/76802 , H01L21/76831 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.
摘要翻译：通过首先形成覆盖导电垫的第一绝缘层来制造半导体存储器。接下来形成和图案位线导电层和第二绝缘层以暴露第一绝缘层的一部分。形成覆盖第一绝缘层的暴露表面的第三绝缘层。露出位线导电层图案的上表面和第三绝缘层的上表面。去除第三绝缘层和第一绝缘层的一部分以暴露导电焊盘。在位线导电层图案和第一绝缘层的侧壁上形成间隔物。分别在位线导电层图案和第一间隔物的侧壁上形成绝缘层图案和第二间隔层，并且形成与导电焊盘接触的导电插塞。

45. 发明授权

US06777341B2 Method of forming a self-aligned contact, and method of fabricating a semiconductor device having a self-aligned contact 有权
标题翻译：形成自对准接触的方法，以及制造具有自对准接触的半导体器件的方法
公开(公告)号：US06777341B2
公开(公告)日：2004-08-17
申请号：US09847289
申请日：2001-05-03
申请人： Kyoung-sub Shin , Ji-soo Kim , Gyung-jin Min , Tae-hyuk Ahn
发明人： Kyoung-sub Shin , Ji-soo Kim , Gyung-jin Min , Tae-hyuk Ahn
IPC分类号： H01L21302
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/10814 , H01L27/10888 , H01L28/91
摘要： In a method of forming a self-aligned contact, gates are formed on a semiconductor substrate in a striped pattern. Bit lines are formed in a striped pattern that extends cross-wise to the gates. The bit lines are isolated from one another by a first interlayer insulation layer. Next, a second interlayer insulation layer is formed between the bit lines, and a photoresist film pattern is formed on the second interlayer insulation layer. The photoresist film pattern is used for forming contact holes extending between the gates down to conductive pads. The contact holes are filled to form conductive plugs that contact the conductive pads. The photoresist film pattern is formed as a series of stripes which extend parallel to the gates. The stripes of photoresist expose segments of the bit lines and the portions of the second interlayer insulation layer disposed directly above the conductive film pads, thereby securing a sufficient alignment margin, and exposing a large underlying area to be etched in forming the contact holes. To form a semiconductor device, a third interlayer insulation layer, an etch stop layer, an oxide layer and a hard mask layer are formed on the conductive plugs. Next, a second photoresist film pattern is formed on the hard mask layer. The hard mask layer and the oxide layer are etched using the second photoresist film pattern as an etching mask until the etch stop layer is exposed. Second contact holes for use in forming capacitor lower electrodes are formed by sequentially removing the exposed etching stop layer and the exposed third interlayer insulation layer using the hard mask layer as an etching mask, until the second contact holes expose the conductive plugs.
摘要翻译：在形成自对准接触的方法中，栅极以条纹图案形成在半导体衬底上。位线以横向延伸到栅极的条纹图案形成。位线通过第一层间绝缘层彼此隔离。接着，在位线之间形成第二层间绝缘层，在第二层间绝缘层上形成光致抗蚀剂膜图案。光致抗蚀剂图案用于形成在栅极之间延伸到导电焊盘的接触孔。接触孔被填充以形成接触导电垫的导电插塞。光致抗蚀剂膜图案形成为平行于栅极延伸的一系列条纹。光致抗蚀剂的条纹将位线的部分和第二层间绝缘层的部分直接设置在导电膜焊盘的正上方，从而确保足够的对准边缘，并且在形成接触孔时暴露待蚀刻的大的下面的区域。为了形成半导体器件，在导电插塞上形成第三层间绝缘层，蚀刻停止层，氧化物层和硬掩模层。接下来，在硬掩模层上形成第二光致抗蚀剂图案。使用第二光致抗蚀剂膜图案作为蚀刻掩模蚀刻硬掩模层和氧化物层，直到暴露出蚀刻停止层。通过使用硬掩模层作为蚀刻掩模依次去除暴露的蚀刻停止层和暴露的第三层间绝缘层，直到第二接触孔露出导电插塞，形成用于形成电容器下电极的第二接触孔。

46. 发明授权

US06653228B2 Method for preparing semiconductor including formation of contact hole using difluoromethane gas 失效
公开(公告)号：US06653228B2
公开(公告)日：2003-11-25
申请号：US09995747
申请日：2001-11-29
申请人： Sung-Gil Choi , Tae-Hyuk Ahn
发明人： Sung-Gil Choi , Tae-Hyuk Ahn
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31144 , H01L21/76831
摘要： A method for forming a contact hole in a semiconductor device includes the steps of forming a polymer layer on an upper portion and a side wall of photo resist mask, while etching an oxide layer under the photoresist mask to form a contact hole that uses an etchant gas comprising CH2F2 gas; and etching the oxide layer while stopping the supply of CH2F2 gas to the etching process.

47. 发明申请

US20100099248A1 Methods of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20100099248A1
公开(公告)日：2010-04-22
申请号：US12588564
申请日：2009-10-20
申请人： Du-Hyun Cho , Tae-Hyuk Ahn , Sang-Sup Jeong , Jin-Hyuk Yoo
发明人： Du-Hyun Cho , Tae-Hyuk Ahn , Sang-Sup Jeong , Jin-Hyuk Yoo
IPC分类号： H01L21/28
CPC分类号： H01L27/11573 , H01L21/28114 , H01L27/105 , H01L27/1052 , H01L29/42376
摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.
摘要翻译：提供了制造半导体器件的方法，所述方法包括在半导体衬底上形成依次层叠的第一电介质层，数据存储层和第二电介质层。具有暴露第二电介质层的第一区域的第一开口的掩模形成在第二电介质层上。形成填充至少一部分第一开口的栅电极。暴露第二电介质层的第二区域的第二开口通过蚀刻掩模形成，使得第二区域与第一区域间隔开。通过依次蚀刻第二介电层和数据存储层的暴露的第二区域来形成第二介质图案和数据存储图案。第二电介质图案形成为具有比栅电极的下表面更大的宽度。

48. 发明申请

US20090206399A1 METHOD OF FORMING A RECESS CHANNEL TRENCH PATTERN, AND FABRICATING A RECESS CHANNEL TRANSISTOR 审中-公开
标题翻译：形成记忆通道图案的方法和制作记录道信道
公开(公告)号：US20090206399A1
公开(公告)日：2009-08-20
申请号：US12430831
申请日：2009-04-27
申请人： Jong-Chul PARK , Yong-Sun KO , Tae-Hyuk AHN
发明人： Jong-Chul PARK , Yong-Sun KO , Tae-Hyuk AHN
IPC分类号： H01L29/78
CPC分类号： H01L29/66621 , H01L21/28123 , H01L21/823412 , H01L21/823437 , H01L27/10808 , H01L27/10876
摘要： A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.
摘要翻译：提供一种形成用于形成凹槽通道晶体管的凹槽沟槽图案的方法。掩模层形成在半导体衬底上，然后将其图案化以暴露具有隔离孔型图案的有源区和相邻器件隔离层的一部分。使用该掩模层，半导体衬底和器件隔离层部分被选择性地和各向异性地蚀刻，从而形成具有隔离孔型图案的凹槽沟槽。掩模层可以被图案化为曲线型。在这种情况下，一次线性部分是弯曲的，以允许由图案化掩模层露出的器件隔离层部分与相邻的有源区域间隔开。然后蚀刻半导体衬底和器件隔离层部分，从而形成具有曲线型图案的凹槽沟槽。

49. 发明申请

US20090102017A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20090102017A1
公开(公告)日：2009-04-23
申请号：US12247315
申请日：2008-10-08
申请人： Yong-kug BAE , Si-hyeung LEE , Tae-hyuk AHN , Seok-hwan OH
发明人： Yong-kug BAE , Si-hyeung LEE , Tae-hyuk AHN , Seok-hwan OH
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10852 , H01L28/91
摘要： A semiconductor device and a method of fabricating a semiconductor device provide high quality cylindrical capacitors. The semiconductor device includes a substrate defining a cell region and a peripheral circuit region, a plurality of capacitors in the cell region, and supports for supporting lower electrodes of the capacitors. The lower electrodes are disposed in a plurality of rows each extending in a first direction. A dielectric layer is disposed on the lower electrodes, and an upper electrode is disposed on the dielectric layer. The supports are in the form of stripes extending longitudinally in the first direction and spaced from each other along a second direction. Each of the supports engages the lower electrodes of a respective plurality of adjacent rows of the lower electrodes. Each one of the supports is also disposed at a different level in the device from the support that is adjacent thereto in the second direction.
摘要翻译：半导体器件和制造半导体器件的方法提供高质量的圆柱形电容器。半导体器件包括限定单元区域和外围电路区域的基板，单元区域中的多个电容器以及用于支撑电容器的下部电极的支撑。下电极配置成沿着第一方向延伸的多列。电介质层设置在下电极上，上电极设置在电介质层上。支撑体是沿着第一方向纵向延伸并且沿着第二方向彼此间隔开的条纹的形式。每个支撑件接合下电极的相应多个相邻行的下电极。每个支撑件还设置在与第二方向相邻的支撑件处于装置中的不同水平处。

50. 发明授权

US07511328B2 Semiconductor device having raised cell landing pad and method of fabricating the same 失效
标题翻译：具有升高电池着陆垫的半导体器件及其制造方法
公开(公告)号：US07511328B2
公开(公告)日：2009-03-31
申请号：US11268551
申请日：2005-11-08
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： H01L27/108
CPC分类号： H01L27/10855 , H01L21/76895
摘要： A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.
摘要翻译：半导体器件及其制造方法具有焊盘延伸部分，该半导体器件包括限定有源区的隔离层和穿过有源区的栅电极。源极区域设置在栅电极的一侧的有源区中，并且在栅电极的第二侧的有源区中设置有漏极区。第一层间绝缘层覆盖半导体衬底。源着陆焊盘电连接到源极区域，并且漏极接地焊盘电连接到漏极区域。垫片延伸部分层压在源着陆垫和排水着陆垫的一个或多个上。焊盘延伸部分具有位于与源着陆焊盘和排水接地焊盘的上表面对应的平面上方的平面中的上表面。

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