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41. 发明授权

US5969992A EEPROM cell using P-well for tunneling across a channel 失效
标题翻译：使用P阱的EEPROM单元进行跨通道的隧穿
公开(公告)号：US5969992A
公开(公告)日：1999-10-19
申请号：US217647
申请日：1998-12-21
申请人： Sunil D. Mehta , Xiao-Yu Li
发明人： Sunil D. Mehta , Xiao-Yu Li
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L27/11558
摘要： An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a P-well of a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.
摘要翻译：描述了通过遍及分离的晶体管通道的整个部分的电子隧道编程和擦除的EEPROM单元。 EEPROM单元具有形成在半导体衬底的P阱中的三个晶体管。三个晶体管是隧道晶体管（NMOS），感测晶体管（NMOS）和读取晶体管（NMOS）。发生电子隧穿，以在浮动栅极和感测通道之间发生足够的电压电势时通过感测隧道氧化物层来编程EEPROM单元。当浮置栅极和隧穿通道之间产生足够的电压电势时，也会发生电子隧穿，以通过隧道氧化物层擦除EEPROM单元。

42. 发明授权

US07078286B1 Process for fabricating a semiconductor device having electrically isolated low voltage and high voltage regions 有权
标题翻译：用于制造具有电隔离的低电压和高电压区域的半导体器件的工艺
公开(公告)号：US07078286B1
公开(公告)日：2006-07-18
申请号：US10928563
申请日：2004-08-27
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232 , H01L27/115 , H01L27/11558
摘要： A process for fabricating a semiconductor device having electrically isolated low voltage and high voltage substrate regions includes low voltage and high voltage trench isolation structures in which a deep portion of the high voltage isolation trench provides electrical isolation in the high voltage regions. The high voltage isolation trench structures include a shallow portion that can be simultaneously formed with the low voltage trench isolation structures. The deep portion of the high voltage isolation trench has a bottom surface and shares a continuous wall surface with the shallow portion that extends from the bottom surface to the principal surface of the substrate. A process for fabricating the device includes the formation of sidewall spacers to define a minimum isolation width between adjacent high voltage nodes.
摘要翻译：一种用于制造具有电隔离的低电压和高电压衬底区域的半导体器件的工艺包括低电压和高电压沟槽隔离结构，其中高压隔离沟槽的深部分在高电压区域中提供电隔离。高电压隔离沟槽结构包括可与低电压沟槽隔离结构同时形成的浅部分。高电压隔离沟槽的深部具有底表面并且具有从底部表面延伸到基底主表面的浅部分的连续壁表面。用于制造该器件的工艺包括形成侧壁间隔物以限定相邻高压节点之间的最小隔离宽度。

43. 发明授权

US06545313B1 EEPROM tunnel window for program injection via P+ contacted inversion 失效
标题翻译： EEPROM隧道窗口通过P +接触反转进行程序注入
公开(公告)号：US06545313B1
公开(公告)日：2003-04-08
申请号：US10211125
申请日：2002-08-02
申请人： Chun Jiang , Robert Tu , Sunil D. Mehta
发明人： Chun Jiang , Robert Tu , Sunil D. Mehta
IPC分类号： H01L29788
CPC分类号： H01L21/28273
摘要： An improved method for fabricating a tunnel oxide window for use in an EEPROM memory cell is provided so as to produce better programming endurance. A P+ implant is provided at the tunnel window edge. During the programming operation, the P+ contacted inversion layer is used instead of the program junction. As a result, there is eliminated the voltage drop in the program junction region so as to improve the efficiency of programming.
摘要翻译：提供了一种用于制造用于EEPROM存储单元的隧道氧化物窗口的改进方法，以便产生更好的编程耐久性。在隧道窗边缘提供P +植入物。在编程操作期间，使用P +接触反转层代替程序结。结果，消除了程序结区域中的电压降，从而提高编程效率。

44. 发明授权

US06472308B1 Borderless vias on bottom metal 失效
公开(公告)号：US06472308B1
公开(公告)日：2002-10-29
申请号：US09949276
申请日：2001-09-07
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76819 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An improved manufacturing process and an improved device made by the process for forming via interconnects between metal layers in a multilevel metallization structure substantially eliminates trench formation during via overetch and exploding vias during via fill. An insulating multilayer structure comprising a conformal oxide, a spin-on layer, and an etch stop layer for the via etch locally planarizes the region adjacent to metal lines before the ILD is deposited and vias are patterned and etched. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.

45. 发明授权

US06214666B1 Method of forming a non-volatile memory device 失效
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US06214666B1
公开(公告)日：2001-04-10
申请号：US09216051
申请日：1998-12-18
申请人： Sunil D. Mehta
发明人： Sunil D. Mehta
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , G11C16/0441 , H01L29/7886 , Y10S438/983
摘要： A method for manufacturing a non-volatile EEPROM memory cell, and a memory cell structure provided by the method. The method comprises the steps of: forming a gate stack on the surface of a substrate; forming a first and a second active regions in the substrate so that the first and second active regions extend to a depth below the surface of the substrate and have a first impurity type and an impurity concentration; and implanting a pocket region of an opposite conductivity type to that of the first or second active region into the surface of the substrate adjacent to the first active region. The step of implanting a pocket region may performed by implanting substantially at an angle non-normal to the surface of the substrate.
摘要翻译：一种用于制造非易失性EEPROM存储单元的方法，以及通过该方法提供的存储单元结构。该方法包括以下步骤：在衬底的表面上形成栅叠层; 在所述衬底中形成第一和第二有源区，使得所述第一和第二有源区延伸到所述衬底的表面下方的深度并且具有第一杂质类型和杂质浓度; 以及将与所述第一或第二有源区的相反导电类型的口袋区域注入到与所述第一有源区相邻的所述衬底的表面中。注入口袋区域的步骤可以通过基本上以不垂直于基底表面的角度注入来进行。

46. 发明授权

US06208559B1 Method of operating EEPROM memory cells having transistors with thin gate oxide and reduced disturb 有权
标题翻译：操作具有具有薄栅极氧化物和减少干扰的晶体管的EEPROM存储单元的方法
公开(公告)号：US06208559B1
公开(公告)日：2001-03-27
申请号：US09441220
申请日：1999-11-15
申请人： Robert H. Tu , Sunil D. Mehta
发明人： Robert H. Tu , Sunil D. Mehta
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10 , H01L27/115
摘要： An improved process of programming and erasing an EEPROM memory cell in an array of identical cells uses a reduced voltage on the write transistor of the cell to be programmed or erased and at the same time applies smaller voltages across the relatively thin oxides of the write transistors of the other cells in the array so as to reduce oxide leakage and damage in those cells but without disturbing the information stored in those cells. The result is the ability to scale down the size of the EEPROM memory cell allowing enhanced economies and permitting faster program, erase and reading speeds.
摘要翻译：编程和擦除相同单元阵列中的EEPROM存储单元的改进过程使用待编程或擦除的单元写入晶体管上的降低的电压，同时在写入晶体管的相对薄的氧化物上施加较小的电压的阵列中的其他电池，以便减少这些电池中的氧化物泄漏和损坏，但是不会干扰存储在这些电池中的信息。结果是能够缩小EEPROM存储单元的尺寸，从而增强经济性，并允许更快的编程，擦除和读取速度。

47. 发明授权

US06172392B2 Boron doped silicon capacitor plate 失效
标题翻译：硼掺杂硅电容器板
公开(公告)号：US06172392B2
公开(公告)日：2001-01-09
申请号：US09280887
申请日：1999-03-29
申请人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
发明人： Christopher O. Schmidt , Sunil D. Mehta , Xiao-Yu Li
IPC分类号： H01L29788
CPC分类号： H01L27/11558 , H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.
摘要翻译：一种利用p型杂质的程序结区域和在其上生长的氧化物的非易失性存储器件。一方面，该装置包括编程结构和通过场氧化物区与所述编程结构分离的程序结。程序结氧化物层覆盖所述程序结区域。在覆盖所述编程结构，所述程序结氧化物层的氧化物上提供浮置栅极，并且在一些实施例中，提供感测晶体管的栅极氧化物。

48. 发明授权

US6087275A Reduction of n-channel parasitic transistor leakage by using low power/low pressure phosphosilicate glass 失效
标题翻译：通过使用低功率/低压磷硅玻璃减少n沟道寄生晶体管泄漏
公开(公告)号：US6087275A
公开(公告)日：2000-07-11
申请号：US843150
申请日：1997-04-26
申请人： Minh Van Ngo , Sunil D. Mehta , Nicholas R. MacCrae
发明人： Minh Van Ngo , Sunil D. Mehta , Nicholas R. MacCrae
IPC分类号： H01L21/316 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/31
CPC分类号： H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/31625 , H01L21/76202 , H01L21/76895 , H01L21/823481
摘要： A method of manufacturing a semiconductor device with increasing threshold voltage for parasitic transistor by forming a low power-low pressure phosphosilicate glass layer on the active regions and the field oxide regions.
摘要翻译：一种通过在有源区域和场氧化物区域上形成低功率 - 低压磷硅玻璃层来制造用于寄生晶体管的阈值电压增加的半导体器件的方法。

49. 发明授权

US6075293A Semiconductor device having a multi-layer metal interconnect structure 有权
标题翻译：具有多层金属互连结构的半导体器件
公开(公告)号：US6075293A
公开(公告)日：2000-06-13
申请号：US263412
申请日：1999-03-05
申请人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
发明人： Xiao-Yu Li , Sunil D. Mehta , Van H. Pham , Amit P. Marathe
IPC分类号： H01L23/532 , H01L23/48
CPC分类号： H01L23/53223 , H01L2924/0002
摘要： A multi-level metal interconnect structure in a semiconductor device includes a plurality of overlying metal layers separated by ILD layers and electrically connected by filled vias in the ILD layers. Each metal layer includes a relatively thick antireflective layer for improved electromigration resistance. Each metal layer also includes a metal lining layer and a metal interconnect layer overlying the metal lining layer. Enhanced electromigration resistance is obtained by forming the antireflective layer to a thickness of no less than the thickness of the metal lining layer. In a preferred embodiment of the invention, the antireflective layer has a thickness of about 1000 angstroms.
摘要翻译：半导体器件中的多级金属互连结构包括由ILD层分离并由ILD层中的填充通孔电连接的多个上覆金属层。每个金属层包括相对较厚的抗反射层，用于改善电迁移阻力。每个金属层还包括覆盖金属衬里层的金属衬里层和金属互连层。通过将抗反射层形成为不小于金属衬里层的厚度的厚度来获得增强的电迁移电阻。在本发明的优选实施例中，抗反射层的厚度为约1000埃。

50. 发明授权

US6064595A Floating gate memory apparatus and method for selected programming thereof 有权
标题翻译：浮栅存储装置及其选择编程方法
公开(公告)号：US6064595A
公开(公告)日：2000-05-16
申请号：US220201
申请日：1998-12-23
申请人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
发明人： Stewart G. Logie , Sunil D. Mehta , Steven J. Fong
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0441 , G11C16/10 , H01L29/7886
摘要： A method of creating a reverse breakdown condition in an array of memory cells arranged in columns and rows in the array, and an array structure are provided. The method comprises the steps of applying a first voltage on a first column connection coupling a first column of said cells, and a second voltage on a second column connection coupling a second column of said cells; and applying a third voltage on a first row connection coupling a first row of said cells, and applying said second voltage on a second row connection coupling a second row of said cells. In this aspect, the difference between the first voltage and the third voltage creates said reverse breakdown condition in at least one cell occupying said first column and first row. In a further aspect, each cell includes a floating gate and the method of the invention includes the step of programming one of said cells by coupling a control voltage to each floating gate. The structure includes a substrate having formed therein at least an Nth or Mth row-wise oriented well, each well isolated from adjacent ones of said wells. Also provided are at least an Nth and Mth word bit line formed by an Nth and Mth impurity regions in said substrate and at least an Nth and Mth array control gate lines. A plurality of memory cells, each cell formed in at least said Nth or Mth row-wise well, is further provided. Each cell comprises a drain, a floating gate, a drain connection one of said Nth or Mth word bit line (WBL), and a substrate well connection to one of said Nth or Mth wells, and a control gate connection to one of said Nth or Mth array control gate lines(ACG).
摘要翻译：提供了在阵列中以行和列排列的存储单元阵列中产生反向故障条件的方法，以及阵列结构。该方法包括以下步骤：在耦合所述单元的第一列的第一列连接上施加第一电压，以及在耦合所述单元的第二列的第二列连接上施加第二电压; 以及在耦合所述单元的第一行的第一行连接上施加第三电压，以及将耦合所述单元的第二行的第二行连接上施加所述第二电压。在这方面，第一电压和第三电压之间的差异在占据所述第一列和第一行的至少一个单元中产生所述反向击穿条件。在另一方面，每个单元包括浮动栅极，并且本发明的方法包括通过将控制电压耦合到每个浮动栅极来编程所述单元之一的步骤。该结构包括在其中形成有至少第N或第M行行取向阱的衬底，每个阱与相邻的所述阱分离。还提供了由所述衬底中的第N和第M杂质区形成的至少第N和第M字位线以及至少第N和第M阵列控制栅极线。还提供多个存储单元，每个单元形成在至少所述第N或第M行列井中。每个单元包括所述第N或第M字位线（WBL）之一的漏极，浮置栅极，漏极连接以及与所述第N或第M阱之一的衬底阱连接，以及到所述第N个或第M阵列控制栅极线（ACG）。

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