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41. 发明授权

US07871921B2 Methods of forming interconnection structures for semiconductor devices 有权
标题翻译：形成半导体器件互连结构的方法
公开(公告)号：US07871921B2
公开(公告)日：2011-01-18
申请号：US11022240
申请日：2004-12-22
申请人： Jin-Taek Park , Jong-Ho Park , Sung-Hoi Hur , Hyun-Suk Kim
发明人： Jin-Taek Park , Jong-Ho Park , Sung-Hoi Hur , Hyun-Suk Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L21/76877 , H01L23/485
摘要： An interconnection structure for a semiconductor device includes an inter-level insulation layer disposed on a semiconductor substrate. First contact constructions penetrate the inter-level insulation layer. Second contact constructions penetrate the inter-level insulation layer. Metal interconnections connect the first contact constructions to the second contact constructions on the inter-level insulation layer. The first contact constructions include first and second plugs stacked in sequence and the second contact constructions include the second plug.
摘要翻译：半导体器件的互连结构包括设置在半导体衬底上的级间绝缘层。第一接触结构穿透层间绝缘层。第二接触构造穿透层间绝缘层。金属互连将第一接触结构连接到层间绝缘层上的第二接触结构。第一接触构造包括依次堆叠的第一和第二插塞，并且第二接触构造包括第二插塞。

42. 发明授权

US07538385B2 Memory device and fabrication method thereof 有权
公开(公告)号：US07538385B2
公开(公告)日：2009-05-26
申请号：US11790047
申请日：2007-04-23
申请人： Yoo-Cheol Shin , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Yoo-Cheol Shin , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954
摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

43. 发明授权

US07391071B2 Nonvolatile memory devices with trenched side-wall transistors and method of fabricating the same 有权
标题翻译：具有沟槽侧壁晶体管的非易失性存储器件及其制造方法
公开(公告)号：US07391071B2
公开(公告)日：2008-06-24
申请号：US11233857
申请日：2005-09-23
申请人： Min-Cheol Park , Sung-Hoi Hur , Jung-Dal Choi , Ji-Hwon Lee
发明人： Min-Cheol Park , Sung-Hoi Hur , Jung-Dal Choi , Ji-Hwon Lee
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/7883
摘要： A nonvolatile memory device includes a semiconductor substrate, a device isolation layer, a tunnel insulation layer, a floating gate, a buried floating gate, and a control gate. A trench is in the substrate that defines an active region of the substrate adjacent to the trench. A device isolation layer is on the substrate along the trench. A tunnel insulation layer is on the active region of the substrate. A floating gate is on the tunnel insulation layer opposite to the active region of the substrate. A buried floating gate is on the device isolation layer in the trench. An intergate dielectric layer is on and extends across the floating gate and the buried floating gate. A control gate is on the intergate dielectric layer and extends across the floating gate and the buried floating gate.
摘要翻译：非易失性存储器件包括半导体衬底，器件隔离层，隧道绝缘层，浮置栅极，埋入浮栅和控制栅极。衬底中的沟槽限定邻近沟槽的衬底的有源区。器件隔离层沿着沟槽在衬底上。隧道绝缘层位于衬底的有源区上。浮动栅极位于与衬底的有源区相对的隧道绝缘层上。埋置的浮动栅极位于沟槽中的器件隔离层上。隔间电介质层在浮栅和埋入浮栅之间并且延伸。控制栅极位于隔间电介质层上，并跨越浮置栅极和埋入浮栅。

44. 发明申请

US20080093677A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080093677A1
公开(公告)日：2008-04-24
申请号：US11616947
申请日：2006-12-28
申请人： Tae Kyung Kim , Sung-Hoi Hur , Chang-Sub Lee , Seung-Chul Lee , Dong-Jun Lee
发明人： Tae Kyung Kim , Sung-Hoi Hur , Chang-Sub Lee , Seung-Chul Lee , Dong-Jun Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00 , H01L21/8238
CPC分类号： H01L27/0883 , H01L21/823412 , H01L29/1033 , H01L29/7833
摘要： Provided are semiconductor devices and methods of fabricating the same. A semiconductor device may include a semiconductor substrate with a device isolation layer defining HVE and HVD active regions. Gate insulation layer patterns may be disposed on the HVE and HVD active regions. Gate electrodes may be disposed on the gate insulation layer patterns to intersect the HVE and HVD active regions and the device isolation layer. An ion implantation layer may be disposed on the semiconductor substrate under the gate electrode of the HVD active region, spaced apart from the device isolation layer, and serves to adjust a threshold voltage.
摘要翻译：提供半导体器件及其制造方法。半导体器件可以包括具有限定HVE和HVD有源区的器件隔离层的半导体衬底。栅极绝缘层图案可以设置在HVE和HVD有源区上。栅极电极可以设置在栅极绝缘层图案上以与HVE和HVD有源区域和器件隔离层相交。离子注入层可以设置在与器件隔离层间隔开的HVD有源区的栅极下方的半导体衬底上，并用于调节阈值电压。

45. 发明授权

US07315055B2 Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices having recessed channels 失效
标题翻译：具有凹陷通道的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅（SONOS）存储器件
公开(公告)号：US07315055B2
公开(公告)日：2008-01-01
申请号：US10999306
申请日：2004-11-30
申请人： Myoung-kwan Cho , Sung-hoi Hur , Eun-suk Cho
发明人： Myoung-kwan Cho , Sung-hoi Hur , Eun-suk Cho
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/7923
摘要： Unit cells of silicon-oxide-nitride-oxide-silicon (SONOS) memory devices are provided. The unit cells include an integrated circuit substrate and a SONOS memory cell on the integrated circuit substrate. The SONOS memory cell includes a source region, a drain region and a gate contact. The integrated circuit substrate defines a trench between the source and drain regions and the gate contact is provided in the trench. A floor of the trench extends further into the integrated circuit substrate than lower surfaces of the source and drain regions. Related methods of fabricating SONOS memory cells are also provided.
摘要翻译：提供了氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）存储器件的单位电池。单元电池包括集成电路基板和集成电路基板上的SONOS存储单元。 SONOS存储单元包括源极区，漏极区和栅极接触。集成电路基板在源极和漏极区域之间限定沟槽，并且在沟槽中设置栅极接触。沟槽的底部比源极和漏极区域的下表面进一步延伸到集成电路衬底内。还提供了制造SONOS存储单元的相关方法。

46. 发明授权

US06903406B2 Cells of nonvolatile memory device with high inter-layer dielectric constant 有权
标题翻译：具有高层间介电常数的非易失性存储器件的单元
公开(公告)号：US06903406B2
公开(公告)日：2005-06-07
申请号：US10346957
申请日：2003-01-17
申请人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , Y10S257/905
摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.
摘要翻译：本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。每个器件隔离层具有突出在半导体衬底上的侧壁。多个字线跨越器件隔离层。隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极顺序堆叠的图案。然后在器件隔离层和控制栅极图案上形成导电层。此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

47. 发明授权

US06797570B2 NAND-type flash memory devices and methods of fabricating the same 有权
标题翻译： NAND型闪存器件及其制造方法
公开(公告)号：US06797570B2
公开(公告)日：2004-09-28
申请号：US10087330
申请日：2002-03-01
申请人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur
发明人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.
摘要翻译：提供了NAND型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

48. 发明授权

US6064590A Non-volatile static random access memory device 失效
标题翻译：非易失性静态随机存取存储器件
公开(公告)号：US6064590A
公开(公告)日：2000-05-16
申请号：US130801
申请日：1998-08-07
申请人： Chul-Hi Han , Sung-Hoi Hur
发明人： Chul-Hi Han , Sung-Hoi Hur
IPC分类号： H01L27/11 , G11C14/00 , G11C16/04
CPC分类号： G11C14/00
摘要： A non-volatile static random access memory device configured by adding a floating gate type metal oxide semiconductor device to an SRAM including a pair of access elements respectively switched on and off in accordance with the state of a signal on an address line and adapted to establish a data transfer path between memory cell and associated negative and positive data lines, and a pair of inverters respectively coupled to the access elements, thereby allowing the SRAM to exhibit non-volatile memory characteristics. The floating gate type MOS device has a silicon substrate, a tunneling oxide film formed over the silicon substrate, a floating gate formed on the tunneling oxide film, an oxide film formed over the floating gate, a control gate formed over the oxide film, and a source and a drain respectively formed in an upper surface of the silicon substrate at both sides of the control gate. The source and drain of the floating gate type MOS device are electrically connected at the source and drain thereof to the input terminals of the inverters of the SRAM, respectively, so that it provides non-volatile memory characteristics to the SRAM by virtue of a difference in threshold voltage caused by charge stored in the floating gate thereof. This non-volatile SRAM device has a high density while exhibiting high-speed operation characteristics.
摘要翻译：一种非易失性静态随机存取存储器件，通过根据地址线上的信号的状态将浮栅型金属氧化物半导体器件添加到包括分别接通和关断的一对存取元件的SRAM，并适于建立存储器单元和相关联的负和正数据线之间的数据传输路径，以及分别耦合到访问元件的一对反相器，从而允许SRAM呈现非易失性存储器特性。浮栅型MOS器件具有硅衬底，在硅衬底上形成的隧道氧化膜，在隧道氧化膜上形成的浮栅，形成在浮栅上的氧化膜，形成在氧化物膜上的控制栅，以及分别形成在控制栅极两侧的硅衬底的上表面中的源极和漏极。浮栅型MOS器件的源极和漏极分别在源极和漏极之间电连接到SRAM的反相器的输入端，使得其通过差异向SRAM提供非易失性存储器特性在由其存储在其浮动栅极中的电荷引起的阈值电压中。这种非易失性SRAM器件具有高密度，同时具有高速操作特性。

49. 发明申请

US20120223379A1 NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120223379A1
公开(公告)日：2012-09-06
申请号：US13407187
申请日：2012-02-28
申请人： Hyun-Sil OH , Sung-Hoi Hur , Dae-Sin Kim
发明人： Hyun-Sil OH , Sung-Hoi Hur , Dae-Sin Kim
IPC分类号： H01L27/105 , H01L21/762
CPC分类号： H01L27/11521 , G11C16/0466
摘要： A non-volatile memory device includes a substrate including a plurality of active regions and a plurality of device isolating trenches formed between a respective one of each of the active regions along a first direction in the substrate. A plurality of gate structures each including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode is formed on the substrate. A first insulating layer pattern is provided within the device isolating trenches. A second insulating layer pattern is formed along an inner surface portion of a gap between the gate structures. An impurity doped polysilicon pattern is formed on the second insulating layer pattern in the gap between the gate structures.
摘要翻译：非易失性存储器件包括：衬底，其包括多个有源区和多个器件隔离沟槽，沿着衬底中的第一方向形成在每个有源区中的相应一个之间。在衬底上形成各自包括隧道绝缘层图案，浮栅电极，电介质层图案和控制栅极电极的多个栅极结构。在器件隔离沟槽内提供第一绝缘层图案。沿着栅极结构之间的间隙的内表面部分形成第二绝缘层图案。在栅极结构之间的间隙中的第二绝缘层图案上形成杂质掺杂多晶硅图案。

50. 发明申请

US20120202335A1 METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES 有权
标题翻译：制造非活性存储器件的方法，包括有源区域和相关器件之间的失调
公开(公告)号：US20120202335A1
公开(公告)日：2012-08-09
申请号：US13300787
申请日：2011-11-21
申请人： Dong-Sik Lee , Jang-Hyun You , Jee-Hoon Han , Young-Woo Park , Sung-Hoi Hur , Sang-Ick Joo
发明人： Dong-Sik Lee , Jang-Hyun You , Jee-Hoon Han , Young-Woo Park , Sung-Hoi Hur , Sang-Ick Joo
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76229 , H01L21/764
摘要： A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.
摘要翻译：制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。沟槽和其间的有源区延伸到衬底的第一和第二器件区域。牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区在第二设备区域中。还讨论了相关的方法和设备。

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