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1. 发明授权

US08084805B2 Three-dimensional microelectronic devices including repeating layer patterns of different thicknesses 有权
标题翻译：三维微电子器件包括不同厚度的重复层图案
公开(公告)号：US08084805B2
公开(公告)日：2011-12-27
申请号：US12420518
申请日：2009-04-08
申请人： Sun-Il Shim , Sung-Hoi Hur , Jin-Ho Kim , Su-Youn Yi
发明人： Sun-Il Shim , Sung-Hoi Hur , Jin-Ho Kim , Su-Youn Yi
IPC分类号： H01L29/76
CPC分类号： H01L27/1158 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.
摘要翻译：垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。第一闪存单元与面相邻，并且最后的闪存单元远离面。闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。支柱包括至少一个斜壁。串中重复层图案的系列中的至少两个具有不同的厚度。还描述了其它垂直微电子器件和相关的制造方法。

2. 发明申请

US20110233636A1 Semiconductor Memory Device and Method of Manufacturing the Same 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20110233636A1
公开(公告)日：2011-09-29
申请号：US13050320
申请日：2011-03-17
申请人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
发明人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures.
摘要翻译：公开了非易失性存储器件和制造非易失性存储器件的方法。非易失性存储器件包括衬底，衬底上的至少两个栅极结构，以及在至少两个栅极结构之间的衬底的部分中的至少一个杂质区域。至少一个杂质区域的中心与至少两个栅极结构之间的区域的中心水平偏移。

3. 发明申请

US20080268595A1 NAND flash memory devices and methods of fabricating the same 失效
标题翻译： NAND闪存器件及其制造方法
公开(公告)号：US20080268595A1
公开(公告)日：2008-10-30
申请号：US12216393
申请日：2008-07-03
申请人： Ji-Hwon Lee , Sung-Hoi Hur
发明人： Ji-Hwon Lee , Sung-Hoi Hur
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.
摘要翻译： NAND包括设置在限定多个有源区的衬底的区域中的器件隔离图案。具有构成单元串的存储器栅极图案的存储晶体管跨过多个有源区。选择晶体管设置在存储晶体管的上方，并且下部插头设置在单元串的每一侧，以电连接单元串和选择晶体管的两侧上的多个有源区。

4. 发明授权

US07411239B2 Nand flash memory devices and methods of fabricating the same 失效
标题翻译： Nand闪存器件及其制造方法
公开(公告)号：US07411239B2
公开(公告)日：2008-08-12
申请号：US11509007
申请日：2006-08-24
申请人： Ji-Hwon Lee , Sung-Hoi Hur
发明人： Ji-Hwon Lee , Sung-Hoi Hur
IPC分类号： H01L27/108
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A NAND includes a device isolation pattern disposed in a region of a substrate defining a plurality of active regions. Memory transistors having memory gate patterns, constituting a cell string, cross the plurality of active regions. Select transistors are disposed over the memory transistors, and lower plugs are disposed on each side of the cell string to electrically connect the plurality of active regions on both sides of the cell string and the select transistors.
摘要翻译： NAND包括设置在限定多个有源区的衬底的区域中的器件隔离图案。具有构成单元串的存储器栅极图案的存储晶体管跨过多个有源区。选择晶体管设置在存储晶体管的上方，并且下部插头设置在单元串的每一侧，以电连接单元串和选择晶体管的两侧上的多个有源区。

5. 发明申请

US20070252194A1 Memory device and fabrication method thereof 有权
公开(公告)号：US20070252194A1
公开(公告)日：2007-11-01
申请号：US11790047
申请日：2007-04-23
申请人： Yoo-Cheol Shin , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Yoo-Cheol Shin , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L27/108 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954
摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.

6. 发明授权

US07259421B2 Non-volatile memory devices having trenches 失效
标题翻译：具有沟槽的非易失性存储器件
公开(公告)号：US07259421B2
公开(公告)日：2007-08-21
申请号：US11020920
申请日：2004-12-23
申请人： Sung-Hoi Hur , Jung-Dal Choi
发明人： Sung-Hoi Hur , Jung-Dal Choi
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a semiconductor substrate having a trench therein. First and second gate patterns are formed on a surface of the substrate adjacent the trench, a respective one of which is on a respective opposing side of the trench. A split source/drain region is formed in the substrate between the first gate pattern and the second gate pattern such that the split source/drain region is divided by the trench. The split source/drain region includes a first source/drain subregion between the first gate pattern and the trench and a second source/drain subregion between the second gate pattern and the trench and spaced apart from the first source/drain subregion. A connecting region is formed in the substrate that extends around the trench from the first source/drain subregion to the second source/drain subregion. Related methods are also discussed.
摘要翻译：半导体存储器件包括其中具有沟槽的半导体衬底。第一和第二栅极图案形成在与沟槽相邻的衬底的表面上，其相应的一个位于沟槽的相应的相对侧上。在第一栅极图案和第二栅极图案之间的衬底中形成分离源极/漏极区域，使得分离源极/漏极区域被沟槽分开。分离源极/漏极区域包括在第一栅极图案和沟槽之间的第一源极/漏极子区域和在第二栅极图案和沟槽之间并与第一源极/漏极子区域间隔开的第二源极/漏极子区域。在从第一源/漏区域到第二源极/漏极子区域的沟槽周围延伸的衬底中形成连接区域。还讨论了相关方法。

7. 发明申请

US20070108498A1 Non-volatile memory devices having floating gates and related methods of forming the same 失效
标题翻译：具有浮动栅极的非易失性存储器件及其相关方法
公开(公告)号：US20070108498A1
公开(公告)日：2007-05-17
申请号：US11594327
申请日：2006-11-08
申请人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
发明人： Joon-Hee Lee , Jong-Ho Park , Jin-Hyun Shin , Sung-Hoi Hur , Yong-Seok Kim , Jong-Won Kim
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括具有单元区域的衬底和在衬底的单元区域上的单元器件隔离层，以限定电池活性区域。浮置栅极可以包括顺序堆叠在单元有源区上的下浮置栅极和上浮置栅极，并且隧道绝缘图案可以在浮栅和电池有源区之间。控制栅极电极可以在浮置栅极上，并且阻挡绝缘图案可以在控制栅电极和浮栅之间。更具体地说，上部浮动栅极可以包括在下部浮动栅极上的平坦部分和从邻近电池器件隔离层的平坦部分的两个边缘向上延伸的一对壁部分。此外，由平坦部分和一对壁部分围绕的空间的上部的宽度可以大于空间的下部的宽度。还讨论了相关方法。

8. 发明申请

US20070063257A1 Nonvolatile memory devices including high-voltage MOS transistors with floated drain-side auxiliary gates and methods of fabricating the same 有权
标题翻译：包括具有浮置漏极侧辅助栅极的高压MOS晶体管的非易失性存储器件及其制造方法
公开(公告)号：US20070063257A1
公开(公告)日：2007-03-22
申请号：US11518724
申请日：2006-09-11
申请人： Sung-Hoi Hur , Young-Min Park , Sang-Bin Song , Min-Cheol Park , Ji-Hwon Lee , Su-Youn Yi , Jang-Min Yoo
发明人： Sung-Hoi Hur , Young-Min Park , Sang-Bin Song , Min-Cheol Park , Ji-Hwon Lee , Su-Youn Yi , Jang-Min Yoo
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L29/7887 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11529
摘要： High-voltage MOS transistors with a floated drain-side auxiliary gate are provided. The high-voltage MOS transistors include a source region and a drain region provided in a semiconductor substrate. A main gate electrode is disposed over the semiconductor substrate between the drain region and the source region. A lower drain-side auxiliary gate and an upper drain-side auxiliary gate are sequentially stacked over the semiconductor substrate between the main gate electrode and the drain region. The lower drain-side auxiliary gate is electrically insulated from the semiconductor substrate, the main gate electrode and the upper drain-side auxiliary gate. Methods of fabricating the high-voltage MOS transistors are also provided.
摘要翻译：提供了具有浮置漏极侧辅助栅极的高压MOS晶体管。高压MOS晶体管包括设置在半导体衬底中的源极区域和漏极区域。主栅极设置在漏区和源区之间的半导体衬底之上。下侧漏极侧辅助栅极和上部漏极侧辅助栅极依次堆叠在主栅极和漏极区域之间的半导体衬底上。下漏极侧辅助栅极与半导体基板，主栅电极和上漏极侧辅助栅极电绝缘。还提供了制造高压MOS晶体管的方法。

9. 发明申请

US20070029603A1 METHOD OF FABRICATING CELL OF NONVOLATILE MEMORY DEVICE WITH FLOATING GATE 有权
标题翻译：具有浮动门的非易失性存储器件的制造方法
公开(公告)号：US20070029603A1
公开(公告)日：2007-02-08
申请号：US11530827
申请日：2006-09-11
申请人： Chang-Hyun LEE , Kyu-Charn PARK , Jeong-Hyuk CHOI , Sung-Hoi HUR
发明人： Chang-Hyun LEE , Kyu-Charn PARK , Jeong-Hyuk CHOI , Sung-Hoi HUR
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , Y10S257/905
摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.
摘要翻译：本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。每个器件隔离层具有突出在半导体衬底上的侧壁。多个字线跨越器件隔离层。隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极顺序堆叠的图案。然后在器件隔离层和控制栅极图案上形成导电层。此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

10. 发明授权

US07122426B2 Method of fabricating cell of nonvolatile memory device with floating gate 有权
标题翻译：具有浮动栅极的非易失性存储器件单元制造方法
公开(公告)号：US07122426B2
公开(公告)日：2006-10-17
申请号：US10788002
申请日：2004-02-25
申请人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Chang-Hyun Lee , Kyu-Charn Park , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11519 , Y10S257/905
摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.
摘要翻译：本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。每个器件隔离层具有突出在半导体衬底上的侧壁。多个字线跨越器件隔离层。隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极顺序堆叠的图案。然后在器件隔离层和控制栅极图案上形成导电层。此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

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