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41. 发明授权

US07890703B2 Cache injection using semi-synchronous memory copy operation 有权
标题翻译：缓存注入使用半同步存储器复制操作
公开(公告)号：US07890703B2
公开(公告)日：2011-02-15
申请号：US12359565
申请日：2009-01-26
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F12/0862 , G06F12/0888 , G06F12/0897 , G06F2212/6028
摘要： A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.
摘要翻译：公开了一种基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。该方法包括确定半同步存储器复制操作的开始。在至少一个高速缓存注入位中检查给定值的半同步存储器复制操作。响应于高速缓存注入位中的给定值，预定数量的目的地数据行被复制到至少一级的高速缓存存储器中。

42. 发明授权

US07882321B2 Validity of address ranges used in semi-synchronous memory copy operations 有权
标题翻译：在半同步存储器复制操作中使用的地址范围的有效性
公开(公告)号：US07882321B2
公开(公告)日：2011-02-01
申请号：US12402904
申请日：2009-03-12
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/02
CPC分类号： G06F12/1441 , G06F12/0888 , G06F12/0897
摘要： A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.
摘要翻译：公开了一种用于保护存储器页面的内容的系统，方法和可读取的计算机。该方法包括确定半同步存储器复制操作的开始。确定正在执行半同步存储器复制操作的地址范围。检测到发出的删除页表条目的指令。所述方法还包括确定所发出的指令是否旨在去除与地址范围中的至少一个地址相关联的页表条目。响应于发出的指令旨在去除页表条目，所发出的指令的执行停止，直到半同步存储器复制操作完成。

43. 发明申请

US20100268790A1 Complex Remote Update Programming Idiom Accelerator 失效
标题翻译：复杂的远程更新编程习惯加速器
公开(公告)号：US20100268790A1
公开(公告)日：2010-10-21
申请号：US12424983
申请日：2009-04-16
申请人： Ravi K. Arimilli , Satya P. Sharma
发明人： Ravi K. Arimilli , Satya P. Sharma
IPC分类号： G06F15/16
CPC分类号： G06F9/5044 , G06F9/3009 , G06F2209/509
摘要： A remote update programming idiom accelerator is configured to detect a complex remote update programming idiom in an instruction sequence of a thread. The complex remote update programming idiom includes a read operation for reading data from a storage location at a remote node, a sequence of instructions for performing an update operation on the data to form result data, and a write operation for writing the result data to the storage location at the remote node. The remote update programming idiom accelerator is configured to determine whether the sequence of instructions is longer than an instruction size threshold and responsive to a determination that the sequence of instructions is not longer than the instruction size threshold, transmit the complex remote update programming idiom to the remote node to perform the update operation on the data at the remote node.
摘要翻译：远程更新编程习惯加速器被配置为检测线程的指令序列中的复杂的远程更新编程习语。复杂的远程更新编程习语包括用于从远程节点的存储位置读取数据的读取操作，用于对数据执行更新操作以形成结果数据的指令序列，以及用于将结果数据写入到远程节点的存储位置。远程更新编程习惯加速器被配置为确定指令序列是否长于指令大小阈值，并且响应于指令序列不长于指令大小阈值的确定，将复杂的远程更新编程成语发送到远程节点对远程节点上的数据执行更新操作。

44. 发明申请

US20090199197A1 Wake-and-Go Mechanism with Dynamic Allocation in Hardware Private Array 有权
标题翻译：在硬件私有阵列中动态分配的唤醒机制
公开(公告)号：US20090199197A1
公开(公告)日：2009-08-06
申请号：US12144011
申请日：2008-06-23
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/50
CPC分类号： G06F9/52 , G06F2209/521
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The wake-and-go mechanism may save the state of the thread in a hardware private array. The hardware private array may comprise a plurality of memory cells embodied within the processor or pervasive logic associated with the bus, for example. Alternatively, the hardware private array may be embodied within logic associated with the wake-and-go storage array.
摘要翻译：为数据处理系统提供了一个唤醒机制。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。唤醒机制可以将线程的状态保存在硬件专用阵列中。例如，硬件私有阵列可以包括体现在处理器内的多个存储器单元或与总线相关联的普遍逻辑。或者，硬件私有阵列可以体现在与唤醒存储阵列相关联的逻辑内。

45. 发明申请

US20090199189A1 Parallel Lock Spinning Using Wake-and-Go Mechanism 有权
标题翻译：使用唤醒机制进行平行锁定旋转
公开(公告)号：US20090199189A1
公开(公告)日：2009-08-06
申请号：US12024327
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/38 , G06F9/461 , G06F9/524
摘要： A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is spinning on a lock. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the lock and sets a lock bit in the wake-and-go array. The thread then goes to sleep until the lock frees. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the thread that is spinning on the lock.
摘要翻译：为数据处理系统提供了一个唤醒机制。唤醒机制识别一个编程习惯，表示一个线程正在旋转锁定。唤醒机制使用与锁相关联的目标地址更新唤醒阵列，并在wake-and-go阵列中设置锁定位。线程然后去睡觉，直到锁释放。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。唤醒机制将这些存储地址与等待目标地址均匀的线程相关联，并可能唤醒正在旋转的线程。

46. 发明授权

US09474500B2 Method and system for transfer of cardiac medical image data files 有权
标题翻译：转移心脏医学图像数据文件的方法和系统
公开(公告)号：US09474500B2
公开(公告)日：2016-10-25
申请号：US13146465
申请日：2010-02-05
申请人： Michael Poon , Satya P. Sharma , Arie Kaufman , Rong Zhao , Jacob Sharony
发明人： Michael Poon , Satya P. Sharma , Arie Kaufman , Rong Zhao , Jacob Sharony
IPC分类号： G06K9/00 , G06K9/36 , A61B6/00 , A61B6/03 , G06F19/00
CPC分类号： A61B6/563 , A61B6/032 , A61B6/503 , G06F19/00 , G06F19/321
摘要： A system and method is provided which allows for the transfer of an image data file such as a medical image data file. Device scan slices of an object are acquired per time point. A portion of the device scan slices of the object, e.g., live body organ, per time point which illustrate a change in the object from a previous time point is selected. At least one optical temporal image in spiral fashion per time interval is formed from the selected portion. The at least one optical temporal image is transmittable as an image data file to a location.
摘要翻译：提供了允许传送诸如医学图像数据文件的图像数据文件的系统和方法。每个时间点获取对象的设备扫描切片。选择器件的一部分扫描对象的切片，例如活体器官，每个时间点示出来自先前时间点的对象的变化。从所选择的部分形成每个时间间隔的螺旋形式的至少一个光学时间图像。所述至少一个光学时间图像可作为图像数据文件发送到位置。

47. 发明授权

US08880853B2 CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock 有权
标题翻译：基于CAM的唤醒式窥探引擎，用于唤醒线程进入目标地址锁中进行睡眠
公开(公告)号：US08880853B2
公开(公告)日：2014-11-04
申请号：US12024327
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/40 , G06F9/52 , G06F9/38 , G06F9/46
CPC分类号： G06F9/52 , G06F9/38 , G06F9/461 , G06F9/524
摘要： A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is spinning on a lock. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the lock and sets a lock bit in the wake-and-go array. The thread then goes to sleep until the lock frees. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an event at the target addresses, and may wake the thread that is spinning on the lock.
摘要翻译：为数据处理系统提供了一个唤醒机制。唤醒机制识别一个编程习惯，表示一个线程正在旋转锁定。唤醒机制使用与锁相关联的目标地址更新唤醒阵列，并在wake-and-go阵列中设置锁定位。线程然后去睡觉，直到锁释放。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。唤醒机制将这些存储地址与等待目标地址处的事件的线程相关联，并且可以唤醒正在旋转的线程。

48. 发明授权

US08788795B2 Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors 有权
标题翻译：编写习语加速器，以检查多处理器的预取指令流
公开(公告)号：US08788795B2
公开(公告)日：2014-07-22
申请号：US12024364
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3806
摘要： A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is coming up in the instruction stream. If the programming idiom accelerator recognizes a programming idiom, the programming idiom accelerator may perform an action to accelerate execution of the programming idiom. In the case of a wake-and-go programming idiom, the programming idiom accelerator may record an entry in a wake-and-go array, for example.
摘要翻译：唤醒机制可能是编程习惯加速器。当处理器获取指令时，编程习惯加速器可以向前看，以确定编程习语是否在指令流中出现。如果编程习惯加速器识别编程习惯，则编程习惯加速器可以执行加速编程习语的执行的动作。在唤醒编程习惯的情况下，编程习惯加速器例如可以记录唤醒阵列中的条目。

49. 发明授权

US08635632B2 High performance and resource efficient communications between partitions in a logically partitioned system 有权
标题翻译：逻辑分区系统中分区之间的高性能和资源高效通信
公开(公告)号：US08635632B2
公开(公告)日：2014-01-21
申请号：US12582812
申请日：2009-10-21
申请人： Rakesh Sharma , Satya P. Sharma
发明人： Rakesh Sharma , Satya P. Sharma
IPC分类号： G06F3/00
CPC分类号： G06F9/5077 , G06F9/455
摘要： A mechanism is provided for communicating between a plurality of applications. An application programming interface (API) associated with an originating application running on a first logical partition in a plurality of logical partitions of a logically partitioned data processing system receives a request to send data to a destination application. The API sends a request to identify a location of the destination application to a virtualization management mechanism. Responsive to receiving a response from the virtualization management mechanism, the API determines whether the location of the destination application is in a second logical partition in the plurality of logical partitions of the logically partitioned data processing system. Responsive to the location being in the second logical partition, the API uses a bypass protocol to send the request from the originating application to the destination application.
摘要翻译：提供了用于在多个应用之间进行通信的机制。与在逻辑分区的数据处理系统的多个逻辑分区中的第一逻辑分区上运行的始发应用相关联的应用编程接口（API）接收向目的地应用发送数据的请求。 API向虚拟化管理机制发送请求以识别目的地应用的位置。响应于从虚拟化管理机制接收到响应，API确定目的地应用的位置是否在逻辑分区数据处理系统的多个逻辑分区中的第二逻辑分区中。响应于位于第二逻辑分区中的位置，API使用旁路协议将请求从发起应用发送到目的地应用。

50. 发明授权

US08452947B2 Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms 有权
标题翻译：硬件唤醒机制和内容可寻址存储器，具有预先读取的指令，以检测编程习惯
公开(公告)号：US08452947B2
公开(公告)日：2013-05-28
申请号：US12024507
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/40
CPC分类号： G06F9/3851 , G06F9/542 , G06F2209/543
摘要： A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom. When the thread reaches a programming idiom, the thread goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an event at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译：为数据处理系统提供硬件唤醒机制。唤醒机制在针对线程正在等待事件的编程习语的线程的指令流中向前看。唤醒机制将针对每个识别的编程习语用与事件相关联的目标地址更新一个唤醒数组。当线程达到编程习惯时，线程进入休眠状态，直到事件发生。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。唤醒机制将这些存储地址与等待目标地址处的事件的线程相关联，并且可以唤醒等待事件的一个或多个线程。

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