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1. 发明授权

US08386822B2 Wake-and-go mechanism with data monitoring 有权
标题翻译：具有数据监控的唤醒机制
公开(公告)号：US08386822B2
公开(公告)日：2013-02-26
申请号：US12024540
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/329 , G06F9/485 , G06F9/542 , G06F2209/544 , Y02D10/24
摘要： A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom, specialized instruction, operating system call, or application programming interface call that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address, expected data value, and comparison type associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, logic associated with the CAM performs a comparison based on the data value being written, expected data value, and comparison type.
摘要翻译：为数据处理系统提供了一个唤醒机制。唤醒机制识别编程成语，专用指令，操作系统调用或应用程序编程接口调用，指示线程正在等待事件。唤醒机制使用目标地址，预期数据值和与事件关联的比较类型来更新唤醒数组。线程然后进入休眠状态直到事件发生。唤醒阵列可以是内容可寻址存储器（CAM）。当在对称多处理（SMP）结构上出现修改CAM中目标地址上的值的事务时，与CAM相关联的逻辑将根据写入的数据值，预期数据值和比较类型进行比较。

2. 发明申请

US20120159126A1 Programming Language Exposing Idiom Calls 失效
标题翻译：编程语言公开习语通话
公开(公告)号：US20120159126A1
公开(公告)日：2012-06-21
申请号：US12024508
申请日：2008-02-01
申请人： Ravi K Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/38
CPC分类号： G06F9/3009 , G06F9/3851
摘要： A programming language may include hint instructions that may notify a programming idiom accelerator that a programming idiom is coming. An idiom begin hint exposes the programming idiom to the programming idiom accelerator. Thus, the programming idiom accelerator need not perform pattern matching or other forms of analysis to recognize a sequence of instructions. Rather, the programmer may insert idiom hint instructions, such as an idiom begin hint, to expose the idiom to the programming idiom accelerator. Similarly, an idiom end hint may mark the end of the programming idiom.
摘要翻译：编程语言可以包括可以通知编程习语加速器编程习语即将到来的提示指令。成语开始提示将编程习语暴露给编程习惯加速器。因此，编程习惯加速器不需要执行模式匹配或其他形式的分析来识别指令序列。相反，程序员可以插入成语提示说明，例如成语开始提示，将习语暴露给编程习惯加速器。类似地，成语结束提示可能标记编程习语的结尾。

3. 发明授权

US08171476B2 Wake-and-go mechanism with prioritization of threads 有权
标题翻译：具有线程优先级的唤醒机制
公开(公告)号：US08171476B2
公开(公告)日：2012-05-01
申请号：US12024669
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： A hardware private array is a thread state storage that is embedded within the processor or within logic associated with a bus or wake-and-go logic. The hardware private array and/or wake-and-go array may have a limited storage area. Therefore, each thread may have an associated priority. If there is insufficient space in the hardware private array, then the wake-and-go mechanism may compare the priority of the thread to the priorities of the threads already stored in the hardware private array and wake-and-go array. If the thread has a higher priority than at least one thread already stored in the hardware private array and wake-and-go array, then the wake-and-go mechanism may remove a lowest priority thread, meaning the thread is removed from hardware private array and wake-and-go array and converted to a flee model.
摘要翻译：硬件私有数组是嵌入在处理器内或与总线或唤醒逻辑相关联的逻辑内的线程状态存储器。硬件私有阵列和/或唤醒阵列可能具有有限的存储区域。因此，每个线程可以具有相关联的优先级。如果硬件私有阵列空间不足，则唤醒机制可将线程的优先级与已存储在硬件专用阵列和唤醒数组中的线程的优先级进行比较。如果线程的优先级高于已经存储在硬件专用阵列和唤醒数组中的至少一个线程，则唤醒机制可能会删除最低优先级的线程，这意味着该线程从硬件私有阵列和唤醒阵列并转换为逃离模型。

4. 发明申请

US20110173630A1 Central Repository for Wake-and-Go Mechanism 有权
标题翻译：唤醒机制中央存储库
公开(公告)号：US20110173630A1
公开(公告)日：2011-07-14
申请号：US12024384
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/48
CPC分类号： G06F9/52 , G06F9/542
摘要： A wake-and-go mechanism is provided with a central repository wake-and-go array for a multiple processor data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread running on a processor within the multiple processor data processing system is waiting for an event. The wake-and-go mechanism updates a central repository wake-and-go array with a target address associated with the event. Each entry in the central repository wake-and-go array may include a thread identification (ID), a central processing unit (CPU) ID, the target address, the expected data, a comparison type, a lock bit, a priority, and a thread state pointer, which is the address at which the thread state information is stored.
摘要翻译：提供了一个唤醒机制，具有用于多处理器数据处理系统的中央存储库唤醒阵列。唤醒机制识别一种编程习语，其指示在多处理器数据处理系统中的处理器上运行的线程正在等待事件。唤醒机制更新了具有与事件相关联的目标地址的中央存储库唤醒数组。中央存储库唤醒阵列中的每个条目可以包括线程标识（ID），中央处理单元（CPU）ID，目标地址，预期数据，比较类型，锁定位，优先级和线程状态指针，其是存储线程状态信息的地址。

5. 发明申请

US20110173419A1 Look-Ahead Wake-and-Go Engine With Speculative Execution 有权
标题翻译：具有推测性执行力的前瞻性唤醒引擎
公开(公告)号：US20110173419A1
公开(公告)日：2011-07-14
申请号：US12024419
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3806
摘要： A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. If a look-ahead polling operation succeeds, the look-ahead wake-and-go engine may record an instruction address for the corresponding idiom so that the wake-and-go mechanism may have the thread perform speculative execution at a time when the thread is waiting for an event. During execution, when the wake-and-go mechanism recognizes a programming idiom, the wake-and-go mechanism may store the thread state in the thread state storage. Instead of putting thread to sleep, the wake-and-go mechanism may perform speculative execution.
摘要翻译：为微处理器提供唤醒机制。唤醒机制在针对线程正在等待事件的编程习语的线程的指令流中向前看。如果先行轮询操作成功，先行后唤醒引擎可以记录相应成语的指令地址，使得唤醒机制可能使线程在线程执行推测执行时正在等待一个事件。在执行期间，当唤醒机制识别出编程习惯时，唤醒机制可以将线程状态存储在线程状态存储器中。唤醒机制可能会执行推测性的执行，而不是让线程睡眠。

6. 发明申请

US20090199197A1 Wake-and-Go Mechanism with Dynamic Allocation in Hardware Private Array 有权
标题翻译：在硬件私有阵列中动态分配的唤醒机制
公开(公告)号：US20090199197A1
公开(公告)日：2009-08-06
申请号：US12144011
申请日：2008-06-23
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/50
CPC分类号： G06F9/52 , G06F2209/521
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The wake-and-go mechanism may save the state of the thread in a hardware private array. The hardware private array may comprise a plurality of memory cells embodied within the processor or pervasive logic associated with the bus, for example. Alternatively, the hardware private array may be embodied within logic associated with the wake-and-go storage array.
摘要翻译：为数据处理系统提供了一个唤醒机制。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。唤醒机制可以将线程的状态保存在硬件专用阵列中。例如，硬件私有阵列可以包括体现在处理器内的多个存储器单元或与总线相关联的普遍逻辑。或者，硬件私有阵列可以体现在与唤醒存储阵列相关联的逻辑内。

7. 发明申请

US20090199189A1 Parallel Lock Spinning Using Wake-and-Go Mechanism 有权
标题翻译：使用唤醒机制进行平行锁定旋转
公开(公告)号：US20090199189A1
公开(公告)日：2009-08-06
申请号：US12024327
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/38 , G06F9/461 , G06F9/524
摘要： A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is spinning on a lock. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the lock and sets a lock bit in the wake-and-go array. The thread then goes to sleep until the lock frees. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the thread that is spinning on the lock.
摘要翻译：为数据处理系统提供了一个唤醒机制。唤醒机制识别一个编程习惯，表示一个线程正在旋转锁定。唤醒机制使用与锁相关联的目标地址更新唤醒阵列，并在wake-and-go阵列中设置锁定位。线程然后去睡觉，直到锁释放。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。唤醒机制将这些存储地址与等待目标地址均匀的线程相关联，并可能唤醒正在旋转的线程。

8. 发明授权

US08516484B2 Wake-and-go mechanism for a data processing system 有权
标题翻译：数据处理系统的唤醒机制
公开(公告)号：US08516484B2
公开(公告)日：2013-08-20
申请号：US12024466
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/542
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The operating system or a background sleeper thread associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译：为数据处理系统提供了一个唤醒机制。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。线程然后进入休眠状态直到事件发生。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。操作系统或后台睡眠线程将这些存储地址与等待目标地址的线程相关联，并且可以唤醒等待事件的一个或多个线程。

9. 发明授权

US08312458B2 Central repository for wake-and-go mechanism 有权
标题翻译：中央存储库，用于唤醒机制
公开(公告)号：US08312458B2
公开(公告)日：2012-11-13
申请号：US12024384
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/52 , G06F9/542
摘要： A wake-and-go mechanism is provided with a central repository wake-and-go array for a multiple processor data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread running on a processor within the multiple processor data processing system is waiting for an event. The wake-and-go mechanism updates a central repository wake-and-go array with a target address associated with the event. Each entry in the central repository wake-and-go array may include a thread identification (ID), a central processing unit (CPU) ID, the target address, the expected data, a comparison type, a lock bit, a priority, and a thread state pointer, which is the address at which the thread state information is stored.
摘要翻译：提供了一个唤醒机制，具有用于多处理器数据处理系统的中央存储库唤醒阵列。唤醒机制识别一种编程习语，其指示在多处理器数据处理系统中的处理器上运行的线程正在等待事件。唤醒机制更新了具有与事件相关联的目标地址的中央存储库唤醒数组。中央存储库唤醒阵列中的每个条目可以包括线程标识（ID），中央处理单元（CPU）ID，目标地址，预期数据，比较类型，锁定位，优先级和线程状态指针，其是存储线程状态信息的地址。

10. 发明授权

US08145849B2 Wake-and-go mechanism with system bus response 有权
标题翻译：具有系统总线响应的唤醒机制
公开(公告)号：US08145849B2
公开(公告)日：2012-03-27
申请号：US12024204
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F12/00
CPC分类号： G06F9/382 , G06F9/3851 , G06F9/528 , G06F2209/521
摘要： A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates a wake-and-go storage array with the target address and snooping the target address on the system bus without data exclusivity. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity.
摘要翻译：为数据处理系统提供了一个唤醒机制。唤醒机制被配置为在系统总线上发出预先加载命令以从目标地址读取数据值并执行比较操作以确定目标地址上的数据值是否指示用于一个线程正在等待发生。响应于比较导致事件未发生的确定，唤醒引导器填充具有目标地址的唤醒存储阵列并且在系统总线上窥探目标地址而没有数据独占性。响应于导致确定事件已经发生的比较，唤醒引导器在系统总线上发出加载命令以从具有数据排他性的目标地址读取数据值。

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