专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08516484B2 Wake-and-go mechanism for a data processing system 有权
标题翻译：数据处理系统的唤醒机制
公开(公告)号：US08516484B2
公开(公告)日：2013-08-20
申请号：US12024466
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/542
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The operating system or a background sleeper thread associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译：为数据处理系统提供了一个唤醒机制。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。线程然后进入休眠状态直到事件发生。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。操作系统或后台睡眠线程将这些存储地址与等待目标地址的线程相关联，并且可以唤醒等待事件的一个或多个线程。

2. 发明授权

US08312458B2 Central repository for wake-and-go mechanism 有权
标题翻译：中央存储库，用于唤醒机制
公开(公告)号：US08312458B2
公开(公告)日：2012-11-13
申请号：US12024384
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46 , G06F13/00
CPC分类号： G06F9/52 , G06F9/542
摘要： A wake-and-go mechanism is provided with a central repository wake-and-go array for a multiple processor data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread running on a processor within the multiple processor data processing system is waiting for an event. The wake-and-go mechanism updates a central repository wake-and-go array with a target address associated with the event. Each entry in the central repository wake-and-go array may include a thread identification (ID), a central processing unit (CPU) ID, the target address, the expected data, a comparison type, a lock bit, a priority, and a thread state pointer, which is the address at which the thread state information is stored.
摘要翻译：提供了一个唤醒机制，具有用于多处理器数据处理系统的中央存储库唤醒阵列。唤醒机制识别一种编程习语，其指示在多处理器数据处理系统中的处理器上运行的线程正在等待事件。唤醒机制更新了具有与事件相关联的目标地址的中央存储库唤醒数组。中央存储库唤醒阵列中的每个条目可以包括线程标识（ID），中央处理单元（CPU）ID，目标地址，预期数据，比较类型，锁定位，优先级和线程状态指针，其是存储线程状态信息的地址。

3. 发明授权

US08145849B2 Wake-and-go mechanism with system bus response 有权
标题翻译：具有系统总线响应的唤醒机制
公开(公告)号：US08145849B2
公开(公告)日：2012-03-27
申请号：US12024204
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F12/00
CPC分类号： G06F9/382 , G06F9/3851 , G06F9/528 , G06F2209/521
摘要： A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates a wake-and-go storage array with the target address and snooping the target address on the system bus without data exclusivity. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity.
摘要翻译：为数据处理系统提供了一个唤醒机制。唤醒机制被配置为在系统总线上发出预先加载命令以从目标地址读取数据值并执行比较操作以确定目标地址上的数据值是否指示用于一个线程正在等待发生。响应于比较导致事件未发生的确定，唤醒引导器填充具有目标地址的唤醒存储阵列并且在系统总线上窥探目标地址而没有数据独占性。响应于导致确定事件已经发生的比较，唤醒引导器在系统总线上发出加载命令以从具有数据排他性的目标地址读取数据值。

4. 发明授权

US08145723B2 Complex remote update programming idiom accelerator 失效
标题翻译：复杂的远程更新编程习惯加速器
公开(公告)号：US08145723B2
公开(公告)日：2012-03-27
申请号：US12424983
申请日：2009-04-16
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F15/16
CPC分类号： G06F9/5044 , G06F9/3009 , G06F2209/509
摘要： A remote update programming idiom accelerator is configured to detect a complex remote update programming idiom in an instruction sequence of a thread. The complex remote update programming idiom includes a read operation for reading data from a storage location at a remote node, a sequence of instructions for performing an update operation on the data to form result data, and a write operation for writing the result data to the storage location at the remote node. The remote update programming idiom accelerator is configured to determine whether the sequence of instructions is longer than an instruction size threshold and responsive to a determination that the sequence of instructions is not longer than the instruction size threshold, transmit the complex remote update programming idiom to the remote node to perform the update operation on the data at the remote node.
摘要翻译：远程更新编程习惯加速器被配置为检测线程的指令序列中的复杂的远程更新编程习语。复杂的远程更新编程习语包括用于从远程节点的存储位置读取数据的读取操作，用于对数据执行更新操作以形成结果数据的指令序列，以及用于将结果数据写入到远程节点的存储位置。远程更新编程习惯加速器被配置为确定指令序列是否长于指令大小阈值，并且响应于指令序列不长于指令大小阈值的确定，将复杂的远程更新编程成语发送到远程节点对远程节点上的数据执行更新操作。

5. 发明授权

US08140801B2 Efficient and flexible memory copy operation 失效
标题翻译：高效灵活的内存复制操作
公开(公告)号：US08140801B2
公开(公告)日：2012-03-20
申请号：US12191655
申请日：2008-08-14
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/3824
摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.
摘要翻译：公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。该方法包括在处理器中接收对半同步存储器复制操作的呼叫。半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。存储器复制操作被放置在队列中以由存储器控制器执行。队列耦合到存储器控制器。随着随后的指令从指令流水线可用，继续执行至少一个后续指令。

6. 发明申请

US20110173632A1 Hardware Wake-and-Go Mechanism with Look-Ahead Polling 有权
标题翻译：硬件唤醒机制与前瞻性轮询
公开(公告)号：US20110173632A1
公开(公告)日：2011-07-14
申请号：US12024703
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/542
摘要： A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism performs a look-ahead polling operation for each of the programming idioms. If each of the look-ahead polling operations fails, then the wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom.
摘要翻译：为数据处理系统提供硬件唤醒机制。唤醒机制在用于编程习惯的线程中前进，表示线程正在等待事件。唤醒机制为每个编程习语执行预先轮询操作。如果每个先行轮询操作失败，则唤醒机制将使用与每个识别的编程习语的事件相关联的目标地址来更新唤醒数组。

7. 发明申请

US20110173631A1 Wake-and-Go Mechanism for a Data Processing System 有权
标题翻译：数据处理系统的唤醒机制
公开(公告)号：US20110173631A1
公开(公告)日：2011-07-14
申请号：US12024466
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/542
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The operating system or a background sleeper thread associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译：为数据处理系统提供了一个唤醒机制。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。线程然后进入休眠状态直到事件发生。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。操作系统或后台睡眠线程将这些存储地址与等待目标地址的线程相关联，并且可以唤醒等待事件的一个或多个线程。

8. 发明申请

US20110173625A1 Wake-and-Go Mechanism with Prioritization of Threads 有权
标题翻译：线程优先级唤醒机制
公开(公告)号：US20110173625A1
公开(公告)日：2011-07-14
申请号：US12024669
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： A hardware private array is a thread state storage that is embedded within the processor or within logic associated with a bus or wake-and-go logic. The hardware private array and/or wake-and-go array may have a limited storage area. Therefore, each thread may have an associated priority. If there is insufficient space in the hardware private array, then the wake-and-go mechanism may compare the priority of the thread to the priorities of the threads already stored in the hardware private array and wake-and-go array. If the thread has a higher priority than at least one thread already stored in the hardware private array and wake-and-go array, then the wake-and-go mechanism may remove a lowest priority thread, meaning the thread is removed from hardware private array and wake-and-go array and converted to a flee model.
摘要翻译：硬件私有数组是嵌入在处理器内或与总线或唤醒逻辑相关联的逻辑内的线程状态存储器。硬件私有阵列和/或唤醒阵列可能具有有限的存储区域。因此，每个线程可以具有相关联的优先级。如果硬件私有阵列空间不足，则唤醒机制可将线程的优先级与已存储在硬件专用阵列和唤醒数组中的线程的优先级进行比较。如果线程的优先级高于已经存储在硬件专用阵列和唤醒数组中的至少一个线程，则唤醒机制可能会删除最低优先级的线程，这意味着该线程从硬件私有阵列和唤醒阵列并转换为逃离模型。

9. 发明申请

US20110173423A1 Look-Ahead Hardware Wake-and-Go Mechanism 有权
标题翻译：前瞻性硬件唤醒机制
公开(公告)号：US20110173423A1
公开(公告)日：2011-07-14
申请号：US12024507
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/542 , G06F2209/543
摘要： A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom. When the thread reaches a programming idiom, the thread goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译：为数据处理系统提供硬件唤醒机制。唤醒机制在针对线程正在等待事件的编程习语的线程的指令流中向前看。唤醒机制将针对每个识别的编程习语用与事件相关联的目标地址更新一个唤醒数组。当线程达到编程习惯时，线程进入休眠状态，直到事件发生。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。唤醒机制将这些存储地址与等待目标地址的线程相关联，并且可以唤醒等待事件的一个或多个线程。

10. 发明申请

US20100269115A1 Managing Threads in a Wake-and-Go Engine 有权
标题翻译：在唤醒引擎中管理线程
公开(公告)号：US20100269115A1
公开(公告)日：2010-10-21
申请号：US12425057
申请日：2009-04-16
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/526 , G06F9/4856 , G06F9/505
摘要： A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism detects a thread running on a first processing unit within a plurality of processing units that is waiting for an event that modifies a data value associated with a target address. The wake-and-go mechanism creates a wake-and-go instance for the thread by populating a wake-and-go storage array with the target address. The operating system places the thread in a sleep state. Responsive to detecting the event that modifies the data value associated with the target address, the wake-and-go mechanism assigns the wake-and-go instance to a second processing unit within the plurality of processing units. The operating system on the second processing unit places the thread in a non-sleep state.
摘要翻译：为数据处理系统提供了一个唤醒机制。唤醒机制检测在等待修改与目标地址相关联的数据值的事件的多个处理单元中的第一处理单元上运行的线程。唤醒机制通过使用目标地址填充一个唤醒存储阵列，为线程创建一个唤醒实例。操作系统将线程置于睡眠状态。响应于检测修改与目标地址相关联的数据值的事件，唤醒机制将唤醒实例分配给多个处理单元内的第二处理单元。第二处理单元上的操作系统将线程置于非睡眠状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式