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1. 发明授权

US08732683B2 Compiler providing idiom to idiom accelerator 有权
标题翻译：编译器提供成语习惯加速器
公开(公告)号：US08732683B2
公开(公告)日：2014-05-20
申请号：US12024347
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/45
CPC分类号： G06F8/4441
摘要： A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is coming up in the instruction stream. If the programming idiom accelerator recognizes a programming idiom, the programming idiom accelerator may perform an action to accelerate execution of the programming idiom. A compiler may recognize programming idioms and expose the programming idioms to the programming idiom accelerator within the resulting machine language instructions.
摘要翻译：唤醒机制可能是编程习惯加速器。当处理器获取指令时，编程习惯加速器可以向前看，以确定编程习语是否在指令流中出现。如果编程习惯加速器识别编程习惯，则编程习惯加速器可以执行加速编程习语的执行的动作。编译器可以识别编程习语，并将编程习语暴露给所得到的机器语言指令中的编程习惯加速器。

2. 发明授权

US08640142B2 Wake-and-go mechanism with dynamic allocation in hardware private array 有权
标题翻译：在硬件私有阵列中动态分配的唤醒机制
公开(公告)号：US08640142B2
公开(公告)日：2014-01-28
申请号：US12144011
申请日：2008-06-23
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F2209/521
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread first starts executing, a wake-and-go mechanism automatically allocates space for thread state in a hardware private array and space for a target address and other information, if any, in a wake-and-go array. If the hardware private array comprises a reserved portion of system memory, then the wake-and-go mechanism may request a sufficient portion of memory to store thread state for the thread. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. When a thread ends execution and is no longer in the run queue of the processor, the wake-and-go mechanism de-allocates the space for the thread state information for that thread.
摘要翻译：为数据处理系统提供了一个唤醒机制。当线程首次开始执行时，唤醒机制会自动为硬件专用阵列中的线程状态分配空间，并为唤醒进程阵列中的目标地址和其他信息（如果有）分配空间。如果硬件私有阵列包括系统存储器的保留部分，则唤醒机制可以请求足够的部分存储器来存储线程的线程状态。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。线程然后进入休眠状态直到事件发生。当线程结束执行并且不再处于处理器的运行队列中时，唤醒机制会为该线程的线程状态信息解除分配空间。

3. 发明授权

US08640141B2 Wake-and-go mechanism with hardware private array 有权
标题翻译：具有硬件私有阵列的唤醒机制
公开(公告)号：US08640141B2
公开(公告)日：2014-01-28
申请号：US12024705
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F2209/521
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The wake-and-go mechanism may save the state of the thread in a hardware private array. The hardware private array may comprise a plurality of memory cells embodied within the processor or pervasive logic associated with the bus, for example. Alternatively, the hardware private array may be embodied within logic associated with the wake-and-go storage array.
摘要翻译：为数据处理系统提供了一个唤醒机制。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。唤醒机制可以将线程的状态保存在硬件专用阵列中。例如，硬件私有阵列可以包括体现在处理器内的多个存储器单元或与总线相关联的普遍逻辑。或者，硬件私有阵列可以体现在与唤醒存储阵列相关联的逻辑内。

4. 发明授权

US08316218B2 Look-ahead wake-and-go engine with speculative execution 有权
标题翻译：具有推测性执行的前瞻式唤醒引擎
公开(公告)号：US08316218B2
公开(公告)日：2012-11-20
申请号：US12024419
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3806
摘要： A wake-and-go mechanism is provided for a microprocessor. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicate that the thread is waiting for an event. if a look-ahead polling operation succeeds, the look-ahead wake-and-go engine may record an instruction address for the corresponding idiom so that the wake-and-go mechanism may have the thread perform speculative execution at a time when the thread is waiting for an event. During execution, when the wake-and-go mechanism recognizes a programming idiom, the wake-and-go mechanism may store the thread state in the thread state storage. Instead of putting the thread to sleep, the wake-and-go mechanism may perform speculative execution.
摘要翻译：为微处理器提供唤醒机制。唤醒机制在用于编程习惯的线程的指令流中预示着线程正在等待事件。如果先行轮询操作成功，则先行唤醒引导引擎可以记录相应成语的指令地址，使得唤醒机制可以使线程在线程执行推测性执行正在等待一个事件。在执行期间，当唤醒机制识别出编程习惯时，唤醒机制可以将线程状态存储在线程状态存储器中。唤醒机制可以执行推测性的执行，而不是让线程睡觉。

5. 发明授权

US08250396B2 Hardware wake-and-go mechanism for a data processing system 有权
标题翻译：数据处理系统的硬件唤醒机制
公开(公告)号：US08250396B2
公开(公告)日：2012-08-21
申请号：US12024595
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F9/542 , G06F9/485 , G06F2209/544
摘要： A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism recognizes a programming idiom that indicates that a thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译：为数据处理系统提供硬件唤醒机制。唤醒机制识别一个编程成语，表示线程正在等待事件。唤醒机制使用与事件相关联的目标地址来更新唤醒数组。线程然后进入休眠状态直到事件发生。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。唤醒机制将这些存储地址与等待目标地址的线程相关联，并且可以唤醒等待事件的一个或多个线程。

6. 发明申请

US20110173417A1 Programming Idiom Accelerators 有权
标题翻译：编程成语加速器
公开(公告)号：US20110173417A1
公开(公告)日：2011-07-14
申请号：US12024364
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3806
摘要： A wake-and-go mechanism may be a programming idiom accelerator. As a processor fetches instructions, the programming idiom accelerator may look ahead to determine whether a programming idiom is coming up in the instruction stream. If the programming idiom accelerator recognizes a programming idiom, the programming idiom accelerator may perform an action to accelerate execution of the programming idiom. In the case of a wake-and-go programming idiom, the programming idiom accelerator may record an entry in a wake-and-go array, for example.
摘要翻译：唤醒机制可能是编程习惯加速器。当处理器获取指令时，编程习惯加速器可以向前看，以确定编程习语是否在指令流中出现。如果编程习惯加速器识别编程习惯，则编程习惯加速器可以执行加速编程习语的执行的动作。在唤醒编程习惯的情况下，编程习惯加速器例如可以记录唤醒阵列中的条目。

7. 发明申请

US20090199184A1 Wake-and-Go Mechanism With Software Save of Thread State 有权
标题翻译：唤醒机制与线程状态的软件保存
公开(公告)号：US20090199184A1
公开(公告)日：2009-08-06
申请号：US12024797
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/461 , G06F2209/521
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. Software may save the state of the thread. The thread is then put to sleep. When the wake-and-go array snoops a kill at a given target address, logic associated with wake-and-go array may generate an exception, which may result in a switch to kernel mode, wherein the operating system performs some action before returning control to the originating process. In this case, the trap results in other software, such as the operating system or background sleeper thread, for example, to reload thread from thread state storage and to continue processing of the active threads on the processor.
摘要翻译：为数据处理系统提供了一个唤醒机制。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。软件可以保存线程的状态。然后线程进入睡眠状态。当唤醒阵列在给定的目标地址上侦听到杀死时，与wake-and-go阵列相关联的逻辑可能会产生异常，这可能导致切换到内核模式，其中操作系统在返回之前执行一些操作控制起源过程。在这种情况下，陷阱导致其他软件，例如操作系统或背景睡眠线程，例如，从线程状态存储重新加载线程并继续处理处理器上的活动线程。

8. 发明授权

US07484062B2 Cache injection semi-synchronous memory copy operation 失效
标题翻译：缓存注入半同步内存复制操作
公开(公告)号：US07484062B2
公开(公告)日：2009-01-27
申请号：US11316070
申请日：2005-12-22
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F12/0862 , G06F12/0888 , G06F12/0897 , G06F2212/6028
摘要： A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.
摘要翻译：公开了一种基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。该方法包括确定半同步存储器复制操作的开始。在至少一个高速缓存注入位中检查给定值的半同步存储器复制操作。响应于高速缓存注入位中的给定值，预定数量的目的地数据行被复制到至少一级的高速缓存存储器中。

9. 发明授权

US07454585B2 Efficient and flexible memory copy operation 失效
标题翻译：高效灵活的内存复制操作
公开(公告)号：US07454585B2
公开(公告)日：2008-11-18
申请号：US11316663
申请日：2005-12-22
申请人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
发明人： Ravi K. Arimilli , Rama K. Govindaraju , Peter H. Hochschild , Bruce G. Mealey , Satya P. Sharma , Balaram Sinharoy
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/3824
摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.
摘要翻译：公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。该方法包括在处理器中接收对半同步存储器复制操作的呼叫。半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。存储器复制操作被放置在队列中以由存储器控制器执行。队列耦合到存储器控制器。随着随后的指令从指令流水线可用，继续执行至少一个后续指令。

10. 发明授权

US08516484B2 Wake-and-go mechanism for a data processing system 有权
标题翻译：数据处理系统的唤醒机制
公开(公告)号：US08516484B2
公开(公告)日：2013-08-20
申请号：US12024466
申请日：2008-02-01
申请人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
发明人： Ravi K. Arimilli , Satya P. Sharma , Randal C. Swanberg
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/542
摘要： A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The operating system or a background sleeper thread associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.
摘要翻译：为数据处理系统提供了一个唤醒机制。当一个线程正在等待一个事件，而不是执行一系列获取和比较序列，线程将更新一个唤醒数组与一个与事件关联的目标地址。线程然后进入休眠状态直到事件发生。唤醒阵列可以是内容可寻址存储器（CAM）。当对称多处理（SMP）结构出现在CAM中的目标地址上修改值时，CAM返回存储目标地址的存储地址列表。操作系统或后台睡眠线程将这些存储地址与等待目标地址的线程相关联，并且可以唤醒等待事件的一个或多个线程。

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