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41. 发明申请

US20100100641A1 SYSTEM AND METHODS FOR ASYNCHRONOUS SYNCHRONIZATION 有权
标题翻译：用于异步同步的系统和方法
公开(公告)号：US20100100641A1
公开(公告)日：2010-04-22
申请号：US12645799
申请日：2009-12-23
申请人： Sean M. QUINLAN , Daniel J. Mendez , Rajiv Joshi , Yuri Ardulov
发明人： Sean M. QUINLAN , Daniel J. Mendez , Rajiv Joshi , Yuri Ardulov
IPC分类号： G06F15/16
CPC分类号： H04L67/1095 , G06F9/52 , G06F17/30578 , Y10S707/99955
摘要： Aspects of the advancement provide for information to be synchronized in an asynchronous manner among two or more computing devices.
摘要翻译：进步的方面提供了在两个或更多个计算设备之间以异步方式同步的信息。

42. 发明申请

US20080105969A1 SEMICONDUCTOR CONSTRUCTIONS AND SEMICONDUCTOR DEVICE FABRICATION METHODS 有权
标题翻译：半导体结构和半导体器件制造方法
公开(公告)号：US20080105969A1
公开(公告)日：2008-05-08
申请号：US11965445
申请日：2007-12-27
申请人： Louis Hsu , Rajiv Joshi , Jack Mandelman
发明人： Louis Hsu , Rajiv Joshi , Jack Mandelman
IPC分类号： H01L23/36 , H01L21/58
CPC分类号： H01L23/3677 , H01L2924/0002 , H01L2924/10158 , Y10S438/928 , Y10S438/96 , Y10S438/977 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.
摘要翻译：一种制造半导体器件的方法包括蚀刻形成在半导体晶片的背面上的衬底，以在衬底中形成凹陷，并且在凹部中形成溅射膜，溅射膜包括具有热膨胀系数的第一材料（ CTE），其至少基本上等于衬底的CTE，以及具有大于衬底的热导率的导热性的第二材料。

43. 发明申请

US20080026512A1 INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF 审中-公开
标题翻译：集成电路芯片与具有混合体积的FETs及其制造方法
公开(公告)号：US20080026512A1
公开(公告)日：2008-01-31
申请号：US11867213
申请日：2007-10-04
申请人： RAJIV JOSHI , Louis Hsu , Oleg Gluschenkov
发明人： RAJIV JOSHI , Louis Hsu , Oleg Gluschenkov
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78654
摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.
摘要翻译：一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

44. 发明申请

US20070257314A1 INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF 有权
公开(公告)号：US20070257314A1
公开(公告)日：2007-11-08
申请号：US11775607
申请日：2007-07-10
申请人： RAJIV JOSHI , Louis Hsu , OLEG GLUSCHENKOV
发明人： RAJIV JOSHI , Louis Hsu , OLEG GLUSCHENKOV
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78654
摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

45. 发明申请

US20070201262A1 Logic SRAM cell with improved stability 审中-公开
标题翻译：逻辑SRAM单元具有改进的稳定性
公开(公告)号：US20070201262A1
公开(公告)日：2007-08-30
申请号：US11363311
申请日：2006-02-27
申请人： Rajiv Joshi , Leland Chang
发明人： Rajiv Joshi , Leland Chang
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C11/413
摘要： A static random access memory (SRAM) cell with improved stability that can handle half select operations. The disclosed cell includes: a pair of cross-coupled inverters coupled to a write bit line via a pass transistor, the pass transistor including a gate coupled to a pseudo write word line; a pair of serially coupled transistors coupled to a read bit line, a gate of a first serially coupled transistor being coupled to a read word line and a gate of a second serially coupled transistor being coupled to the pair of cross-coupled inverters; and a word line driver having an output coupled to the pseudo write word line and an input coupled to a write word line, the word line driver being controllable by a bit select input.
摘要翻译：具有改进稳定性的静态随机存取存储器（SRAM）单元，可以处理半选择操作。所公开的单元包括：一对交叉耦合的反相器，其经由传输晶体管耦合到写入位线，所述传输晶体管包括耦合到伪写入字线的栅极; 耦合到读位线的一对串联耦合晶体管，耦合到读字线的第一串联耦合晶体管的栅极和耦合到所述一对交叉耦合反相器的第二串联耦合晶体管的栅极; 以及字线驱动器，其具有耦合到所述伪写入字线的输出和耦合到写入字线的输入，所述字线驱动器可由位选择输入控制。

46. 发明申请

US20070195617A1 Methods and apparatus for read/write control and bit selection with false read suppression in an SRAM 有权
标题翻译：用于读/写控制和位选择的方法和装置，在SRAM中具有伪读取抑制
公开(公告)号：US20070195617A1
公开(公告)日：2007-08-23
申请号：US11356627
申请日：2006-02-17
申请人： Rajiv Joshi
发明人： Rajiv Joshi
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/418
摘要： Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit comprises one or more transistors controlled by a write control gate signal to prevent data from being read from one or more data cells during a write operation. The transistors can comprise, for example, a pair of gated transistors controlled by the write control gate signal. The write control gate signal prevents data from being read from one or more data cells while the write control gate signal is in a predefined state.
摘要翻译：在SRAM中提供读/写控制和位读取抑制的方法和装置。根据本发明的一个方面，提供了一种用于SRAM的比特选择电路。所公开的位选择电路包括由写控制门信号控制的一个或多个晶体管，以防止在写操作期间从一个或多个数据单元读取数据。晶体管可以包括例如由写入控制栅极信号控制的一对门控晶体管。写控制门信号防止在写控制门信号处于预定状态时从一个或多个数据单元读取数据。

47. 发明申请

US20070086232A1 Ring oscillator row circuit for evaluating memory cell performance 有权
标题翻译：用于评估存储单元性能的环形振荡器行电路
公开(公告)号：US20070086232A1
公开(公告)日：2007-04-19
申请号：US11250019
申请日：2005-10-13
申请人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Yuen Chan , Anirudh Devgan
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C29/50012
摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
摘要翻译：用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

48. 发明申请

US20070058448A1 Bitline variable methods and circuits for evaluating static memory cell dynamic stability 失效
公开(公告)号：US20070058448A1
公开(公告)日：2007-03-15
申请号：US11225571
申请日：2005-09-13
申请人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C11/41 , G11C29/006 , G11C29/50 , G11C2029/1204 , G11C2029/5002
摘要： Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.

49. 发明申请

US20070049007A1 Interconnect structure and method for forming the same 有权
标题翻译：互连结构及其形成方法
公开(公告)号：US20070049007A1
公开(公告)日：2007-03-01
申请号：US11216198
申请日：2005-08-31
申请人： Chih-Chao Yang , Louis Hsu , Rajiv Joshi
发明人： Chih-Chao Yang , Louis Hsu , Rajiv Joshi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/76805 , H01L21/76808 , H01L21/76831 , H01L21/76844 , H01L21/76846 , H01L21/76849 , H01L21/76855 , Y10S438/964
摘要： An interconnect structure and a method for forming the same are described. Specifically, under the present invention, a gouge is created within a via formed in the interconnect structure before any trenches are formed. This prevents the above-mentioned trench damage from occurring. That is, the bottom surface of the trenches will have a roughness of less than approximately 20 nm, and preferably less than approximately 10 nm. In addition to the via, gouge and trench(es), the interconnect structure of the present invention includes at least two levels of metal wiring. Further, in a typical embodiment, the interconnect structure utilizes any dielectrics having a dielectric constant no greater than approximately 5.0.
摘要翻译：描述了互连结构及其形成方法。具体地说，在本发明中，在形成任何沟槽之前，在互连结构中形成的通孔内形成一个沟槽。这防止了上述的沟槽损坏发生。也就是说，沟槽的底表面将具有小于约20nm，优选小于约10nm的粗糙度。除了通孔，沟槽和沟槽之外，本发明的互连结构还包括至少两层金属布线。此外，在典型的实施例中，互连结构利用介电常数不大于约5.0的任何电介质。

50. 发明申请

US20060192612A1 Capacitor reliability for multiple-voltage power supply systems 失效
公开(公告)号：US20060192612A1
公开(公告)日：2006-08-31
申请号：US11065840
申请日：2005-02-25
申请人： Louis Hsu , Rajiv Joshi , Jack Mandelman
发明人： Louis Hsu , Rajiv Joshi , Jack Mandelman
IPC分类号： H03K5/00
CPC分类号： H02M3/07
摘要： A capacitor circuit having improved reliability includes at least first and second capacitors, a first terminal of the first capacitor connecting to a first source providing a first voltage, a first terminal of the second capacitor connecting to a second source providing a second voltage, the first voltage being greater than the second voltage. The capacitor further includes a voltage comparator having a first input for receiving a voltage representative of the first voltage, a second input for receiving a third voltage provided by a third source, and an output for generating a control signal. The control signal is a function of a difference between the voltage representative of the first voltage and the third voltage. A switch is connected to second terminals of the first and second capacitors. The switch is selectively operable in one of at least a first mode and a second mode in response to the control signal, wherein in the first mode the switch is operative to connect the first and second capacitors together in parallel, and in the second mode the switch is operative to connect the first and second capacitors together in series. The first mode is indicative of the voltage representative of the first voltage being less than or about equal to the third voltage, and the second mode is indicative of the voltage representative of the first voltage being greater than the third voltage.

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