专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080105898A1 FET Channel Having a Strained Lattice Structure Along Multiple Surfaces 审中-公开
标题翻译：具有沿多个表面的应变晶格结构的FET通道
公开(公告)号：US20080105898A1
公开(公告)日：2008-05-08
申请号：US11969992
申请日：2008-01-07
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L29/778
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SiXGe1−x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和Si X 1 x 1-x x，其中78

2. 发明申请

US20070224801A1 Dielectric interconnect structures and methods for forming the same 有权
标题翻译：介电互连结构及其形成方法
公开(公告)号：US20070224801A1
公开(公告)日：2007-09-27
申请号：US11390390
申请日：2006-03-27
申请人： Chih-Chao Yang , Louis Hsu , Rajiv Joshi
发明人： Chih-Chao Yang , Louis Hsu , Rajiv Joshi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76814 , H01L21/76826 , H01L21/76843 , H01L21/76844 , H01L21/76846
摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.
摘要翻译：提供介电互连结构及其形成方法。具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上表面。在典型的实施例中，通过用气体离子等离子体（例如，Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）。在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

3. 发明申请

US20070058466A1 Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability 失效
标题翻译：用于评估静态存储单元动态稳定性的内部非对称方法和电路
公开(公告)号：US20070058466A1
公开(公告)日：2007-03-15
申请号：US11225652
申请日：2005-09-13
申请人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
发明人： Rajiv Joshi , Qiuyi Ye , Anirudh Devgan
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/006 , G11C29/12005 , G11C29/24 , G11C2029/5002
摘要： Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.
摘要翻译：用于评估静态存储单元动态稳定性的内部非对称方法和电路为提高存储器阵列的性能提供了超越现有水平/产量的机制。通过改变静态随机存取存储器（SRAM）存储单元的内部对称性，操作单元并观察不对称操作引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。或者或组合地，可以改变单元的输出处的负载以影响电池的性能。可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

4. 发明申请

US20070018257A1 Electronic circuit having variable biasing 失效
标题翻译：具有可变偏置的电子电路
公开(公告)号：US20070018257A1
公开(公告)日：2007-01-25
申请号：US11184698
申请日：2005-07-19
申请人： Rajiv Joshi
发明人： Rajiv Joshi
IPC分类号： H01L29/76
CPC分类号： G11C11/413 , G11C7/1051 , G11C7/1078
摘要： Techniques are provided for selectively biasing wells in a circuit, such as a Complementary Metal Oxide Semiconductor (CMOS) circuit, that has two types of transistors, one type formed on a substrate and another type formed on the wells. For example, the circuit can be a memory circuit, and the selective well bias can be changed depending on whether a READ or WRITE operation is being conducted. In another aspect, cells in a memory circuit can be subjected to variable bias depending on conditions, such as, again, whether a READ or WRITE operation is underway.
摘要翻译：提供了用于选择性地偏置诸如互补金属氧化物半导体（CMOS）电路的电路中的阱的技术，其具有两种类型的晶体管，一种类型形成在衬底上，另一种类型形成在阱上。例如，电路可以是存储器电路，并且可以根据是否正在进行READ或WRITE操作来改变选择阱偏置。在另一方面，存储器电路中的单元可以根据诸如再次READ或WRITE操作正在进行的条件经受可变偏置。

5. 发明申请

US20060279334A1 SINGLE SUPPLY LEVEL CONVERTER 有权
标题翻译：单电源电平转换器
公开(公告)号：US20060279334A1
公开(公告)日：2006-12-14
申请号：US11466754
申请日：2006-08-23
申请人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
发明人： Anthony Correale , Rajiv Joshi , David Kung , Zhigang Pan , Ruchir Puri
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0948
摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.
摘要翻译：用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。

6. 发明申请

US20060109733A1 High performance register file with bootstrapped storage supply and method of reading data thereform 有权
标题翻译：具有引导存储供应的高性能寄存器文件和数据读取方法
公开(公告)号：US20060109733A1
公开(公告)日：2006-05-25
申请号：US10996311
申请日：2004-11-22
申请人： Rajiv Joshi , Azeez Bhavnagarwala
发明人： Rajiv Joshi , Azeez Bhavnagarwala
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C8/16
摘要： A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses.
摘要翻译：多端口寄存器文件，包括一个或多个多端口寄存器文件的集成电路（IC）芯片以及从多端口寄存器文件读取数据的方法。在多端口寄存器文件中的存储锁存器的供应在访问期间选择性地被引导到电源电压之上。

7. 发明申请

US20050275977A1 Multi-level power supply system for a complementary metal oxide semiconductor circuit 有权
标题翻译：用于互补金属氧化物半导体电路的多电平供电系统
公开(公告)号：US20050275977A1
公开(公告)日：2005-12-15
申请号：US10867094
申请日：2004-06-14
申请人： Rajiv Joshi , Louis Hsu
发明人： Rajiv Joshi , Louis Hsu
IPC分类号： G06F1/26 , G11C5/14 , G11C11/4074 , H02H7/00
CPC分类号： G11C11/4074 , G06F1/26 , G11C5/14 , Y10T307/305
摘要： There is provided a method for managing a multi-level power supply. The method includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2
摘要翻译：提供了一种用于管理多电平电源的方法。该方法包括将较低电压电源总线的电压电平（Vs 1）与较高电压电源总线的电压电平（Vs 2）进行比较，以及如果Vs 2将电流从低电压电源总线路由到较高电压电源总线

8. 发明申请

US20050063232A1 Integrated circuit chip with improved array stability 失效
标题翻译：集成电路芯片具有改进的阵列稳定性
公开(公告)号：US20050063232A1
公开(公告)日：2005-03-24
申请号：US10950940
申请日：2004-09-27
申请人： Yuen Chan , Rajiv Joshi , Donald Plass
发明人： Yuen Chan , Rajiv Joshi , Donald Plass
IPC分类号： G11C5/06 , G11C8/08 , G11C11/00 , G11C11/413
CPC分类号： G11C8/08 , G11C11/412 , G11C11/417
摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.
摘要翻译：可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。正常基极FET具有基极阈值，并且定制的FET具有高于阈值。在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

9. 发明申请

US20050017377A1 FET channel having a strained lattice structure along multiple surfaces 有权
标题翻译： FET通道沿着多个表面具有应变格子结构
公开(公告)号：US20050017377A1
公开(公告)日：2005-01-27
申请号：US10626760
申请日：2003-07-21
申请人： Rajiv Joshi , Richard Williams
发明人： Rajiv Joshi , Richard Williams
IPC分类号： H01L20060101 , H01L21/336 , H01L21/8244 , H01L21/84 , H01L27/01 , H01L27/11 , H01L27/12 , H01L29/06 , H01L29/786 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/785 , H01L21/84 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/42392 , H01L29/66795 , H01L29/78687 , Y10S257/903
摘要： A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78
摘要翻译： FinFET 10的通道16具有沟道芯24和沟道封套32，每个沟道芯32由限定不同晶格结构的半导体材料制成以利用应变硅特性。栅极通过栅极电介质耦合到沟道封套。示例性材料是Si和SixGe1-x，其中78

10. 发明授权

US06788112B1 High performance dual-stage sense amplifier circuit 失效
标题翻译：高性能双级读出放大器电路
公开(公告)号：US06788112B1
公开(公告)日：2004-09-07
申请号：US10436229
申请日：2003-05-12
申请人： Yuen H. Chan , Rajiv Joshi , Antonio R. Pelella , John R. Rawlins , Jatinder K. Wadhwa
发明人： Yuen H. Chan , Rajiv Joshi , Antonio R. Pelella , John R. Rawlins , Jatinder K. Wadhwa
IPC分类号： G01R1900
CPC分类号： G11C11/419 , G11C7/062 , G11C7/065
摘要： A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.
摘要翻译：一种用于存储器件的读出放大器，包括：第一感测级，包括分别可操作地连接到第一感测线和第二感测线的第一感测装置和第二感测装置，以减小第一感测线和第二感测线上的电容性负载线。感测装置的源极端子连接到可切换的电流接收器，其漏极端子连接到第二感测级的输入端。感测放大器还包括第二感测级，其包括响应于第一感测级的交叉耦合的反相器，第二感测级由响应于所选择的延迟的感测使能信号和响应于第二感测级的输出驱动器激活。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式