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41. 发明授权

US06727568B2 Semiconductor device having a shallow trench isolation and method of fabricating the same 有权
公开(公告)号：US06727568B2
公开(公告)日：2004-04-27
申请号：US10105544
申请日：2002-03-25
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L2900
CPC分类号： H01L29/518 , H01L21/28123 , H01L21/28167 , H01L21/28211 , H01L21/76202 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L29/42368 , H01L29/513 , H01L29/7835
摘要： The present invention includes a semiconductor device having a shallow trench isolation and a method of fabricating the same. The semiconductor device includes a gate electrode being arranged to cross over the active region. An oxide pattern is interposed between the active region and the edge of the gate electrode. The oxide pattern defines a channel region under the gate electrode. A lightly doped diffusion layer is formed in the active region downward and outward from the oxide pattern, and a heavy doped diffusion layer is formed in a predetermined region of the active region and surrounded by the lightly doped diffusion layer. In the method of fabricating the semiconductor substrate, a trench isolation layer is formed at a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary lightly doped diffusion layers are formed in a line to cross over the active region. Then, oxide patterns are formed to cover at least the preliminary lightly doped diffusion layers. The oxide pattern defines a channel region. A gate oxide layer is formed on the channel region and a gate electrode is formed to cover the channel region and to cross over the active region. The edge of the gate electrode is over the oxide pattern. A heavy doped diffusion layer is formed in the active region of both regions of a gate electrode and shallower than the lightly doped diffusion layer.

42. 发明授权

US06468099B2 Semiconductor device fabricating method 有权
公开(公告)号：US06468099B2
公开(公告)日：2002-10-22
申请号：US09941307
申请日：2001-08-29
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L218238
CPC分类号： H01L21/76202 , H01L21/76224 , H01L21/823462 , H01L21/823481 , Y10S438/981
摘要： A method of fabricating a semiconductor device applies a LOCOS profile characteristic to an edge portion of an STI in a HV region to thereby lower compressive stress that is concentrated on the side of the STI. A field oxide film is formed so that only edge portions of HV region (active region II) may be in contact with a comparatively stiff STI, and then, a thick gate oxide film is formed on the HV region by utilizing a nitride film as a mask. After the nitride film as a mask is removed, a thin gate oxide film is formed on a LV region (an active region I in which a thin gate oxide film is formed). As a result, a thinning phenomenon of a gate oxide film at an edge portion of STI is prevented that otherwise would occur when the gate oxide film for HV grows in a normal STI structure by utilizing a nitride film as a mask. The present invention also prevents compromise of the operational characteristics of a resulting transistor, which otherwise would be caused by the concentration of electric field and by the hump phenomenon.

43. 发明授权

US06319654B1 Process for forming a photoresist pattern by top surface imaging process 失效
标题翻译：通过顶表面成像工艺形成光致抗蚀剂图案的工艺
公开(公告)号：US06319654B1
公开(公告)日：2001-11-20
申请号：US09566290
申请日：2000-05-05
申请人： Myoung Soo Kim , Jae Chang Jung , Hyung Gi Kim , Ki Ho Baik
发明人： Myoung Soo Kim , Jae Chang Jung , Hyung Gi Kim , Ki Ho Baik
IPC分类号： G03F740
CPC分类号： G03F7/38 , G03F7/0045 , G03F7/038 , G03F7/265 , Y10S430/168
摘要： The present invention relates to a process for forming a photoresist pattern by employing a silylation process, and particularly to a method for forming a photoresist pattern according to a top surface imaging (TSI) process using a photoresist composition comprising a cross-linker having a cross-linker monomer of the following Chemical Formula 1 or 2. The photoresist composition containing a polymer of the above cross-linker monomer is preferably used in a TSI process which has been optimized by controlling the conditions of each step, such as temperature and time, thereby obtaining an ultrafine pattern that can be more efficiently applied to a 4 G or 16 G DRAM semiconductor fabrication process: wherein, R1, R2, R3, R5, R6, R7, R, m and n are as defined in the specification attached hereto.
摘要翻译：本发明涉及一种通过使用甲硅烷化方法形成光致抗蚀剂图案的方法，特别涉及一种使用光致抗蚀剂组合物的顶表面成像（TSI）方法形成光致抗蚀剂图案的方法，所述光致抗蚀剂组合物包含交联剂含有上述交联剂单体的聚合物的光致抗蚀剂组合物优选用于通过控制各步骤的条件如温度和时间而优化的TSI方法，从而获得可以更有效地应用于4G或16G DRAM半导体制造工艺的超精细图案：其中，R1，R2，R3，R5，R6，R7，R，m和n如本文所附的说明书中所定义。。

44. 发明授权

US06312868B1 Photoresist cross-linker and photoresist composition comprising the same 失效
标题翻译：光阻抗交联剂和包含其的光致抗蚀剂组合物
公开(公告)号：US06312868B1
公开(公告)日：2001-11-06
申请号：US09501096
申请日：2000-02-09
申请人： Keun Kyu Kong , Jae Chang Jung , Myoung Soo Kim , Hyoung Gi Kim , Hyeong Soo Kim , Ki Ho Baik
发明人： Keun Kyu Kong , Jae Chang Jung , Myoung Soo Kim , Hyoung Gi Kim , Hyeong Soo Kim , Ki Ho Baik
IPC分类号： G03F7004
CPC分类号： G03F7/0045 , G03F7/038
摘要： The present invention is directed to photoresist cross-linkers selected from the group consisting of a cross-linker monomer represented by following Chemical Formula 1, and homopolymers and copolymers thereof. Such cross-linkers are suitable for use in photolithography processes employing KrF(248nm), ArF(193nm), E-beam, ion-beam or EUV light sources. wherein X1 and X2 individually represent CH2, CH2CH2, O or S; p and s individually represent an integer from 0 to 5; q is 0 or 1; R′ and R″ independently represent hydrogen or methyl; R represents straight or branched C1-10 alkyl, straight or branched C1-10 ether, straight or branched C1-10 ester, straight or branched C1-10 ketone, straight or branched C1-10 carboxylic acid, straight or branched C1-10 acetal, straight or branched C1-10 alkyl including at least one hydroxyl group, straight or branched C1-10 ether including at least one hydroxyl group, straight or branched C1-10 ester including at least one hydroxyl group, straight or branched C1-10 ketone including at least one hydroxyl group, straight or branched C1-10 carboxylic acid including at least one hydroxyl group, and straight or branched C1-10 acetal including at least one hydroxyl group; R1 and R2 independently represent hydrogen, straight or branched C1-10 alkyl, straight or branched C1-10 ester, straight or branched C1-10 ketone, straight or branched C1-10 carboxylic acid, straight or branched C1-10 acetal, straight or branched C1-10 alkyl including at least one hydroxyl group, straight or branched C1-10 ester including at least one hydroxyl group, straight or branched C1-10 ketone including at least one hydroxyl group, straight or branched C1-10 carboxylic acid including at least one hydroxyl group, and straight or branched C1-10 acetal including at least one hydroxyl group.
摘要翻译：本发明涉及选自由以下化学式1表示的交联剂单体和其均聚物和共聚物的光致抗蚀剂交联剂。这种交联剂适用于采用KrF（248nm），ArF（193nm），电子束，离子束或EUV光源的光刻工艺.X1和X2分别表示CH2，CH2CH2，O或S; p和s各自表示0至5的整数; q为0或1; R'和R“独立地表示氢或甲基; R代表直链或支链C 1-10烷基，直链或支链C1-10醚，直链或支链C1-10酯，直链或支链C 1-10酮，直链或支链C 1-10羧酸，直链或支链C 1-10缩醛包括至少一个羟基的直链或支链C 1-10烷基，包括至少一个羟基的直链或支链C 1-10醚，包括至少一个羟基的直链或支链C 1-10酯，直链或支链C 1-10酮包括至少一个羟基，包括至少一个羟基的直链或支链C 1-10羧酸，和包含至少一个羟基的直链或支链C 1-10缩醛; R 1和R 2独立地表示氢，直链或支链C 1-10烷基，直链或支链C 1-10酯，直链或支链C 1-10酮，直链或支链C 1-10羧酸，直链或支链C 1-10缩醛，直链或包括至少一个羟基的支链C 1-10烷基，包括至少一个羟基的直链或支链C 1-10酯，包括至少一个羟基，直链或支链C 1-10羧酸的直链或支链C 1-10酮包括至少一个羟基，以及包含至少一个羟基的直链或支链C 1-10缩醛。

45. 发明授权

US08416599B2 Metal oxide semiconductor (MOS) field effect transistor having trench isolation region and method of fabricating the same 有权
标题翻译：具有沟槽隔离区域的金属氧化物半导体（MOS）场效应晶体管及其制造方法
公开(公告)号：US08416599B2
公开(公告)日：2013-04-09
申请号：US12498652
申请日：2009-07-07
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： G11C11/00
CPC分类号： H01L21/823481 , H01L29/78
摘要： A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor substrate to define the active region. A source region and a drain region are spaced apart from each other within the active region with a channel region disposed between the source region and the drain region. A gate electrode crosses over the channel region between the source region and the drain region, and a gate insulating layer is disposed between the gate electrode and the channel region. An edge insulating layer thicker than the gate insulating layer is disposed on a lower surface of the gate electrode around the boundary of the trench isolation region and the active region.
摘要翻译：在金属氧化物半导体（MOS）场效应晶体管中，可以防止在沟槽隔离区域和有源区域的边界上产生的漏电流，并提供其制造方法。晶体管包括设置在半导体衬底的预定部分中以限定有源区的沟槽隔离区。源极区域和漏极区域在有源区域内彼此间隔开，沟道区域设置在源极区域和漏极区域之间。栅电极跨越源极区域和漏极区域之间的沟道区域，栅极绝缘层设置在栅电极和沟道区域之间。在沟槽隔离区域和有源区域的边界周围的栅电极的下表面上设置比栅绝缘层厚的边缘绝缘层。

46. 发明申请

US20100155856A1 Transistor, a transistor arrangement and method thereof 有权
公开(公告)号：US20100155856A1
公开(公告)日：2010-06-24
申请号：US12659107
申请日：2010-02-25
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L29/7833 , H01L29/41758 , H01L29/66575
摘要： A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.

47. 发明授权

US07696054B2 Transistor, a transistor arrangement and method thereof 有权
标题翻译：晶体管，晶体管结构及其方法
公开(公告)号：US07696054B2
公开(公告)日：2010-04-13
申请号：US11802004
申请日：2007-05-18
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/41758 , H01L29/66575
摘要： A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.
摘要翻译：提供一种晶体管，晶体管结构及其方法。示例性方法可以包括确定晶体管的栅极宽度是否已被调整; 以及如果所述确定步骤确定所述晶体管的栅极宽度，则基于所述调整的栅极宽度来调整所述晶体管的高浓度杂质掺杂区域和所述晶体管的器件隔离层之间的距离。示例性晶体管可以包括限定第一有源区的第一器件隔离层，具有第一栅极宽度并与第一有源区交叉的第一栅极线，首先在第一有源区中形成的第一低浓度杂质掺杂区和第一栅极线的第二面和形成在低浓度杂质掺杂区域中的第一较高浓度杂质掺杂区，并且不与栅极线和器件隔离层接触。

48. 发明授权

US06720667B2 Semiconductor device having align key for defining active region and method for manufacturing the same 有权
标题翻译：具有用于定义有源区域的对准键的半导体器件及其制造方法
公开(公告)号：US06720667B2
公开(公告)日：2004-04-13
申请号：US10307806
申请日：2002-12-02
申请人： Myoung-soo Kim
发明人： Myoung-soo Kim
IPC分类号： H01L23544
CPC分类号： H01L23/544 , H01L21/823493 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an align key, which is simultaneously formed by implanting ions before defining an active region, for a precise alignment with a preformed well on a semiconductor substrate when forming a photoresist pattern for defining the active region, and a method for manufacturing the same are provided The semiconductor device includes the align key formed of a first recess having a first depth from a surface of a semiconductor substrate in a scribe line region of the semiconductor substrate, and a second step portion formed by a second recess having a second depth, which is less than or equal to the first depth, from the surface of the semiconductor substrate in a well region of the semiconductor substrate.
摘要翻译：一种具有对准键的半导体器件，其在形成用于限定有源区域的光致抗蚀剂图案之前通过在限定有源区域之前注入离子而与半导体衬底上的预制阱精确对准而同时形成，以及制造方法半导体器件包括由半导体衬底的划线区域中的半导体衬底的表面具有第一深度的第一凹部形成的对准键和由具有第二深度的第二凹部形成的第二阶梯部分，其在半导体衬底的阱区中从半导体衬底的表面小于或等于第一深度。

49. 发明授权

US06482565B1 Photoresist cross-linker and photoresist composition comprising the same 失效
标题翻译：光阻抗交联剂和包含其的光致抗蚀剂组合物
公开(公告)号：US06482565B1
公开(公告)日：2002-11-19
申请号：US09448964
申请日：1999-11-24
申请人： Jae Chang Jung , Keun Kyu Kong , Myoung Soo Kim , Hyoung Gi Kim , Hyeong Soo Kim , Ki Ho Baik
发明人： Jae Chang Jung , Keun Kyu Kong , Myoung Soo Kim , Hyoung Gi Kim , Hyeong Soo Kim , Ki Ho Baik
IPC分类号： G03F7004
CPC分类号： C07D407/12 , C07D317/12 , C07D319/06
摘要： The present invention relates to a cross-linker for use in a photoresist which is suitable for a photolithography process using KrF (248 ru), ArF (193 nm), E-beam, ion beam or EUV light source. According to the present invention, preferred cross-linkers comprise a copolymer having repeating units derived from: (i) a compound represented by following Chemical Formula 1 and/or (ii) one or more compound(s) selected from the group consisting of acrylic acid, methacrylic acid and maleic anhydride. wherein, R1, R2 and R individually represent straight or branched C1-10 alkyl, straight or branched C1-10 ester, straight or branched C1-10 ketone, straight or branched C1-10 carboxylic acid, straight or branched C1-10 acetal, straight or branched C1-10 alkyl including at least one hydroxyl group, straight or branched C1-10 ester including at least one hydroxyl group, straight or branched C1-10 ketone including at least one hydroxyl group, straight or branched C1-10 carboxylic acid including at least one hydroxyl group, and straight or branched C1-10 acetal including at least one hydroxyl group; R3 represents hydrogen or methyl; m represents 0 or 1; and n represents a number of 1 to 5.
摘要翻译：本发明涉及用于光致抗蚀剂的交联剂，其适用于使用KrF（248uR），ArF（193nm），电子束，离子束或EUV光源的光刻工艺。根据本发明，优选的交联剂包含具有衍生自以下的重复单元的共聚物：（i）由以下化学式1表示的化合物和/或（ii）一种或多种选自丙烯酸的化合物酸，甲基丙烯酸和马来酸酐。其中R1，R2和R各自表示直链或支链C1-10烷基，直链或支链C1-10酯，直链或支链C1-10酮，直链或支链C1-10羧酸，包括至少一个羟基的直链或支链C 1-10烷基，包括至少一个羟基的直链或支链C 1-10烷基，包括至少一个羟基的直链或支链C 1-10酮，包含至少一个羟基的直链或支链C 1-10羧酸，和包含至少一个羟基的直链或支链C 1-10缩醛; R3表示氢或甲基; m表示0或1; n表示1〜5的数。

50. 发明授权

US06448130B1 Method of selectively forming silicide film of merged DRAM and Logic 失效
标题翻译：选择性地形成合并DRAM和逻辑的硅化物膜的方法
公开(公告)号：US06448130B1
公开(公告)日：2002-09-10
申请号：US09941345
申请日：2001-08-29
申请人： Myoung-Soo Kim
发明人： Myoung-Soo Kim
IPC分类号： H01L218247
CPC分类号： H01L27/10894 , H01L21/76832 , H01L21/76837 , H01L21/823814 , H01L21/823835 , H01L27/10873
摘要： Disclosed is a method of selectively forming a silicide film of merged DRAM logic by which active regions of a logic side are entirely changed into a silicidation state without adding a separate photoresist patterning process even though there exist any regions in which the space between gates is somewhat narrower than in a DRAM cell forming region, and an etch stopper film of SiON material that is needed in the formation of deep contacts can be applied to a MDL process having dual gate in mass production.
摘要翻译：公开了一种选择性地形成合并的DRAM逻辑的硅化物膜的方法，即使存在门之间的空间有些区域，逻辑侧的有源区域也完全改变为硅化状态而不添加单独的光刻胶图案化工艺比DRAM单元形成区域窄，并且形成深触点所需的SiON材料的蚀刻停止膜可以应用于具有双栅极的大批量生产的MDL工艺。

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