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41. 发明申请

US20070206399A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070206399A1
公开(公告)日：2007-09-06
申请号：US11682478
申请日：2007-03-06
申请人： Eiichi Makino , Koji Hosono , Kazushige Kanda , Shigeo Ohshima
发明人： Eiichi Makino , Koji Hosono , Kazushige Kanda , Shigeo Ohshima
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/025 , G11C5/063 , G11C16/0483 , H01L2224/06155 , H01L2224/06156 , H01L2224/48227 , H01L2924/15311
摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.
摘要翻译：一种具有第一存储单元阵列的非易失性半导体存储器件，包括形成在半导体衬底的第一区域中的多个电重新编程和可擦除非易失性半导体存储单元，第二存储单元阵列包括多个电重编程和可擦除非易失性半导体存储单元形成在与所述半导体衬底的所述第一区域不同的第二区域中，所述第一和第二存储单元阵列沿第一方向布置;以及第一焊盘区段，用于向所述第一存储单元阵列和所述第二存储单元阵列输入数据并输出数据所述第一焊盘部分具有沿垂直于所述第一方向的第二方向布置在所述第一存储单元阵列和所述第二存储单元阵列之间的多个焊盘。

42. 发明申请

US20070008803A1 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US20070008803A1
公开(公告)日：2007-01-11
申请号：US11521694
申请日：2006-09-15
申请人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
发明人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C5/14
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/20 , G11C16/20 , G11C16/30
摘要： A semiconductor device of this invention includes an initialization circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, and a status setting unit for setting the status. of the semiconductor device to “busy” during a period in which the initialization circuit performs initialization.
摘要翻译：本发明的半导体器件包括用于根据电源电压的电平初始化预定电路的初始化电路和用于设置状态的状态设置单元。在初始化电路进行初始化的期间内变为“忙”。

43. 发明申请

US20060208777A1 Semiconductor device for generating power on reset signal 失效
标题翻译：用于产生上电复位信号的半导体器件
公开(公告)号：US20060208777A1
公开(公告)日：2006-09-21
申请号：US11376416
申请日：2006-03-16
申请人： Masaki Ichikawa , Kazushige Kanda
发明人： Masaki Ichikawa , Kazushige Kanda
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24
摘要： A reference voltage generating circuit receives a power supply voltage and generates a reference voltage. A reference voltage level guarantee circuit generates a sense signal when the circuit senses that a value of the reference voltage has reached a predetermined value. A power supply voltage sensing circuit has a voltage comparator circuit which compares a voltage obtained by dividing a power supply voltage with the reference voltage and outputs a power ON reset signal. An operation of the voltage comparator circuit is controlled based on a sense signal. When the value of the power supply voltage increases and the value of the reference voltage reaches a predetermined value, the voltage comparator circuit operates, and a power ON reset signal is outputted in response to a result of comparison between a divisional voltage and the reference voltage.
摘要翻译：参考电压产生电路接收电源电压并产生参考电压。当电路感测到参考电压的值已经达到预定值时，参考电压电平保证电路产生感测信号。电源电压检测电路具有电压比较器电路，其将通过将电源电压分压获得的电压与参考电压进行比较，并输出电源接通复位信号。基于感测信号来控制电压比较器电路的操作。当电源电压值增加并且参考电压的值达到预定值时，电压比较器电路工作，并且响应于分压与参考电压之间的比较结果而输出电源复位信号。

44. 发明申请

US20060092724A1 Semiconductor memory device with MOS transistors each having floating gate and control gate 失效
标题翻译：具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极
公开(公告)号：US20060092724A1
公开(公告)日：2006-05-04
申请号：US11169633
申请日：2005-06-30
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C29/00
CPC分类号： G11C29/846 , G11C8/18 , G11C16/0433 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/808
摘要： A semiconductor memory device includes a row address transition detector. The semiconductor memory device remedies a fault by replacing a column in a memory cell array with a redundancy bit line. The row address transition detector detects a change in a row address signal for selecting the row direction of the memory cell array. Only when a change in the row address signal is detected by the row address transition detector, the redundancy bit line is sensed.
摘要翻译：半导体存储器件包括行地址转换检测器。半导体存储器件通过用冗余位线替换存储单元阵列中的列来补救故障。行地址转换检测器检测用于选择存储单元阵列的行方向的行地址信号的变化。只有当行地址转换检测器检测到行地址信号的变化时，才检测冗余位线。

45. 发明授权

US07016241B2 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
公开(公告)号：US07016241B2
公开(公告)日：2006-03-21
申请号：US11052558
申请日：2005-02-07
申请人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
发明人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C7/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/20 , G11C16/20 , G11C16/30
摘要： A semiconductor device of this invention includes an initialization circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, and a status setting unit for setting the status of the semiconductor device to “busy” during a period in which the initialization circuit performs initialization.

46. 发明申请

US20050146970A1 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used 有权
标题翻译：半导体器件，非易失性半导体存储器，包括多个半导体器件或非易失性半导体存储器的系统，包括半导体器件或非易失性半导体存储器的电卡，以及可以使用该电卡的电子器件
公开(公告)号：US20050146970A1
公开(公告)日：2005-07-07
申请号：US11052558
申请日：2005-02-07
申请人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
发明人： Kazushige Kanda , Koichi Kawai , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C16/06 , G11C7/10 , G11C7/20 , G11C16/00 , G11C16/20 , G11C16/30 , G11C29/04 , H03K17/22 , G11C7/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/20 , G11C16/20 , G11C16/30
摘要： A semiconductor device of this invention includes an initialization circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, and a status setting unit for setting the status of the semiconductor device to “busy” during a period in which the initialization circuit performs initialization.
摘要翻译：本发明的半导体器件包括：初始化电路，用于根据电源电压的电平初始化预定电路;以及状态设置单元，用于在初始化期间将半导体器件的状态设置为“忙” 电路执行初始化。

47. 发明授权

US06674318B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06674318B2
公开(公告)日：2004-01-06
申请号：US10231082
申请日：2002-08-30
申请人： Kazushige Kanda , Tamio Ikehashi , Ken Takeuchi , Kenichi Imamiya
发明人： Kazushige Kanda , Tamio Ikehashi , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G05F110
CPC分类号： G11C7/062
摘要： A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit. In order to provide a voltage trimming function, a voltage intended to be set in an external terminal may be given from the outside to deactivate a feedback system of the limiter circuit to operate a resistance value of the limiter circuit to detect and store a limiter flag. Thus, there is provided a semiconductor integrated circuit capable of simply monitoring the output voltage state of an internal power supply circuit by the external terminal and easily trimming an internal voltage.
摘要翻译：半导体集成电路包括限幅电路，用于输出电压确定标志，以便将升压电路的升压电压设定为预定值;以及监视电路，用于监视限幅器电路的监视节点以输出监视信号用于稳定第一外部端子的升压电压。监控电路通过比较器检测在限制器电路的操作开始之后电压确定标志从“H”到“L”的第一电平变化，供给外部电源电压和外部参考电压给出第二和第三外部端子，然后在限幅器电路的操作期间输出用于保持恒定逻辑电平的监视信号。为了提供电压调整功能，可以从外部给出旨在设置在外部端子中的电压以去激活限幅器电路的反馈系统，以操作限幅器电路的电阻值以检测和存储限幅器标志。因此，提供了能够简单地通过外部端子监视内部电源电路的输出电压状态并容易地修整内部电压的半导体集成电路。

48. 发明授权

US06359494B2 Semiconductor integrated circuit device having an oscillation circuit using reference current source independent from influence of variation of power supply voltage and threshold voltage of transistor 失效
公开(公告)号：US06359494B2
公开(公告)日：2002-03-19
申请号：US09756804
申请日：2001-01-10
申请人： Kazushige Kanda , Hiroshi Nakamura
发明人： Kazushige Kanda , Hiroshi Nakamura
IPC分类号： H03L500
CPC分类号： G05F3/247 , G05F3/262 , H03K3/0231
摘要： According to the present invention, the semiconductor integrated circuit including the reference current generating circuit free from both the influence of a power supply voltage and the influence of the variation of the threshold voltage of the transistors related to the generation of the reference current. In the reference current generating circuit, a P-channel MOS transistor (Qp1), a N-channel MOS transistor (Qn1), a resistor element (R1), and a N-channel MOS transistor (Qn2) are connected in series between the power supply voltage and the ground. The gate and the drain of the N-channel MOS transistor (Qn2) are connected by a short circuit to output the reference current Iref from a transistor (Qn6) through the resistor element. The integrated circuit is provided with a level shifter connected to the reference current generating circuit such that the threshold voltages of the N-channel transistors (Qn1, Qn2) are added to a reference voltage Vref by N-channel transistors (Qn3, Qn4) in the level shifter, and the resultant reference voltage Vref is applied to the gate of the N-channel transistors (Qn1).

49. 发明授权

US08644051B2 Semiconductor memory device and control method of the same 有权
标题翻译：半导体存储器件及其控制方法相同
公开(公告)号：US08644051B2
公开(公告)日：2014-02-04
申请号：US13230156
申请日：2011-09-12
申请人： Kazushige Kanda
发明人： Kazushige Kanda
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C7/1021 , G11C7/22 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/51 , G11C2213/71 , G11C2213/72
摘要： According to one embodiment, a semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, and a data input/output circuit includes a first address buffer and a second address buffer configured to store a first address and a second address of the plurality of memory cells, and a controller configured to perform control to time-divisionally output the first address and the second address to a first address bus and a second address bus in data input/output.
摘要翻译：根据一个实施例，半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括多个存储单元，多个存储单元阵列堆叠在半导体衬底上以形成三维结构，以及数据输入/输出电路包括：第一地址缓冲器和第二地址缓冲器，被配置为存储多个存储器单元的第一地址和第二地址;以及控制器，被配置为执行控制以将第一地址和第二地址时分输出到第一地址地址总线和数据输入/输出中的第二个地址总线。

50. 发明授权

US08593852B2 Test device and test method for resistive random access memory and resistive random access memory device 有权
标题翻译：电阻随机存取存储器和电阻随机存取存储器件的测试装置和测试方法
公开(公告)号：US08593852B2
公开(公告)日：2013-11-26
申请号：US13238479
申请日：2011-09-21
申请人： Kazuaki Kawaguchi , Kazushige Kanda
发明人： Kazuaki Kawaguchi , Kazushige Kanda
IPC分类号： G11C11/00
CPC分类号： G11C29/56 , G11C11/16 , G11C13/00 , G11C29/50012 , G11C29/56012
摘要： According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.
摘要翻译：根据实施例，在恒定周期改变的第一写入使能信号和在字线的激活/停止控制和位线的激活/去激活控制之间的限制时间的时间部分发生变化的第二写使能信号是多个核心控制信号，其中核心控制信号改变的时间间隔基于输入的第一写入使能信号和第二写入使能信号而局部地短于第一写入使能信号的周期并且通过使用所生成的核心控制信号来执行电阻性随机存取存储器的操作验证，从而局部地和任意地调整任意测试周期中的周期时间。

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