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41. 发明授权

US06492238B1 Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit 有权
标题翻译：具有凸起的外部基极的双极晶体管在集成的BiCMOS电路中制造
公开(公告)号：US06492238B1
公开(公告)日：2002-12-10
申请号：US09887310
申请日：2001-06-22
申请人： David C. Ahlgren , Gregory G. Freeman , Feng-Yi Huang , Adam D. Ticknor
发明人： David C. Ahlgren , Gregory G. Freeman , Feng-Yi Huang , Adam D. Ticknor
IPC分类号： H01L2100
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623
摘要： A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.
摘要翻译：用于形成具有凸起的外部基极，发射极和与具有栅极的CMOS电路集成的集电极的双极晶体管的工艺。提供具有CMOS和双极区域的中间半导体结构。在双极区域内提供本征基层。基底氧化物跨越形成，牺牲发射极堆叠硅层沉积在CMOS和双极区两者上。施加光致抗蚀剂以保护双极区域，并且蚀刻该结构以从CMOS区域去除牺牲层，使得双极区域上的牺牲层的顶表面基本上与CMOS区域的顶表面齐平。最后，沉积抛光停止层，其具有穿过适于随后的化学机械抛光（CMP）的CMOS和双极区域的基本平坦的顶表面，以形成凸起的外在基体。

42. 发明授权

US06472288B2 Method of fabricating bipolar transistors with independent impurity profile on the same chip 失效
标题翻译：在同一芯片上制造具有独立杂质分布的双极型晶体管的方法
公开(公告)号：US06472288B2
公开(公告)日：2002-10-29
申请号：US09733330
申请日：2000-12-08
申请人： Gregory G. Freeman , K. T. Schonenberg , Kenneth J. Stein , Seshadri Subbanna
发明人： Gregory G. Freeman , K. T. Schonenberg , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L21331
CPC分类号： H01L27/0823 , H01L21/8222 , Y10S438/933
摘要： Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.
摘要翻译：不同设计的双极晶体管，特别是针对不同高频应用优化的设计，通过用于锗，硼和/或碳的不同材料浓度分布的用于外延生长的单独的基底层形成工艺在相同的衬底上形成。通过使用可以选择性地蚀刻到硅上的蚀刻停止来避免通过包括相应的集电极区域的硅衬底的蚀刻来促进单个生长层通过低温工艺的外延生长。退火处理可以在各基底层的生长之间进行和/或在所有晶体管基本上完成之后集体执行。

43. 发明授权

US07741186B2 Creating increased mobility in a bipolar device 失效
标题翻译：在双极设备中增加移动性
公开(公告)号：US07741186B2
公开(公告)日：2010-06-22
申请号：US11946940
申请日：2007-11-29
申请人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
发明人： Dureseti Chidambarrao , Gregory G. Freeman , Marwan H. Khater
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L29/7378
摘要： The mobility of charge carriers in a bipolar (BJT) device is increased by creating compressive strain in the device to increase mobility of electrons in the device, and creating tensile strain in the device to increase mobility of holes in the device. The compressive and tensile strain are created by applying a stress film adjacent an emitter structure of the device and atop a base film of the device. In this manner, the compressive and tensile strain are located in close proximity to an intrinsic portion of the device. A suitable material for the stress film is nitride. The emitter structure may be “T-shaped”, having a lateral portion atop an upright portion, a bottom of the upright portion forms a contact to the base film, and the lateral portion overhangs the base film.
摘要翻译：双极（BJT）器件中的载流子的迁移率通过在器件中产生压缩应变以增加器件中电子的迁移率而增加，并且在器件中产生拉伸应变以增加器件中的孔的移动性。通过在装置的发射极结构附近施加应力膜并且在器件的基底上方施加应力膜来产生压缩和拉伸应变。以这种方式，压缩和拉伸应变位于设备本身部分附近。适用于应力膜的材料是氮化物。发射体结构可以是“T形”，其具有在直立部分顶部的侧面部分，直立部分的底部形成与基底膜的接触，并且侧向部分悬垂在基底膜上。

44. 发明授权

US07615457B2 Method of fabricating self-aligned bipolar transistor having tapered collector 有权
标题翻译：制造具有锥形集电极的自对准双极晶体管的方法
公开(公告)号：US07615457B2
公开(公告)日：2009-11-10
申请号：US12220521
申请日：2008-07-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
IPC分类号： H01L21/265 , H01L27/102
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.
摘要翻译：提供了一种用于制造双极晶体管的方法，该双极晶体管包括具有上部基本上平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁的锥形，即截头锥形收集器基座，上表面具有比下表面小得多的面积。收集器基座可以形成在暴露在通过第一和第二覆盖介质区域延伸的开口内的集电极有源区域的表面上，其中开口限定第一和第二电介质区域的垂直对齐的边缘。

45. 发明申请

US20090073758A1 SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS 审中-公开
标题翻译：具有不对称浮动体态栅极晶体管的SRAM电池
公开(公告)号：US20090073758A1
公开(公告)日：2009-03-19
申请号：US11857757
申请日：2007-09-19
申请人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
发明人： Gregory G. Freeman , Qingqing Liang , Mario M. Pelella , Carl J. Radens , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/34 , H01L21/00
CPC分类号： G11C11/412
摘要： The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate transistor, and a second pass-gate transistor. The first pass-gate transistor is connected to a first side of the SRAM cell, wherein the first pass-gate transistor comprises a first drain region and a first source region. The second pass-gate transistor is connected to a second side of the SRAM cell, wherein the second side is opposite the first side. The second pass-gate transistor comprises a second source region and a second drain region. Furthermore, the first source region and/or the second source region comprise a xenon implant. The first drain region and the second drain region each lack a xenon implant.
摘要翻译：本发明的实施例提供具有非对称浮体通过栅极晶体管的SRAM单元。更具体地，半导体器件包括SRAM单元，第一通过栅极晶体管和第二通过栅极晶体管。第一栅极晶体管连接到SRAM单元的第一侧，其中第一栅极晶体管包括第一漏极区域和第一源极区域。第二通栅晶体管连接到SRAM单元的第二侧，其中第二侧与第一侧相对。第二通栅晶体管包括第二源区和第二漏区。此外，第一源区和/或第二源区包括氙植入物。第一漏区和第二漏区各自缺少氙植入物。

46. 发明申请

US20080318373A1 Method of fabricating self-aligned bipolar transistor having tapered collector 有权
标题翻译：制造具有锥形集电极的自对准双极晶体管的方法
公开(公告)号：US20080318373A1
公开(公告)日：2008-12-25
申请号：US12220521
申请日：2008-07-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory G. Freeman , David R. Greenberg , Marwan H. Khater , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A method is provided for making a bipolar transistor which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The collector pedestal can be formed on a surface of a collector active region exposed within an opening extending through first and second overlying dielectric regions, where the opening defines vertically aligned edges of the first and second dielectric regions.
摘要翻译：提供了一种用于制造双极晶体管的方法，该双极晶体管包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有比下表面小得多的面积。收集器基座可以形成在暴露在通过第一和第二覆盖介质区域延伸的开口内的集电极有源区域的表面上，其中开口限定第一和第二电介质区域的垂直对齐的边缘。

47. 发明申请

US20080128861A1 METHODS TO IMPROVE THE SiGe HETEROJUNCTION BIPOLAR DEVICE PERFORMANCE 失效
标题翻译：改善SiGe异性双极性器件性能的方法
公开(公告)号：US20080128861A1
公开(公告)日：2008-06-05
申请号：US11555906
申请日：2006-11-02
申请人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
发明人： Omer H. Dokumaci , Gregory G. Freeman , Marwan H. Khater , Rajendran Krishnasamy , Kathryn T. Schonenberg
IPC分类号： H01L29/73
CPC分类号： H01L29/7378 , H01L29/0821 , H01L29/66242
摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.
摘要翻译：提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

48. 发明申请

US20050233535A1 Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same 失效
公开(公告)号：US20050233535A1
公开(公告)日：2005-10-20
申请号：US11150894
申请日：2005-06-13
申请人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
发明人： Gregory G. Freeman , Marwan H. Khater , Francois Pagette
IPC分类号： H01L29/737 , H01L21/331 , H01L21/8222 , H01L29/10 , H01L29/732 , H01L21/328 , H01L29/70
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrinsic base to the emitter is accomplished by forming the extrinsic base in two regions. First, a first material of silicon or polysilicon having a first doping concentration is provided to form an outer extrinsic base region. Then a first opening is formed in the first material layer by lithography within which a dummy emitter pedestal is formed, which results in forming a trench between the sidewall of the first opening and the dummy pedestal. A second material of a second doping concentration is then provided inside the trench forming a distinct inner extrinsic base extension region to self-align the raised extrinsic base edge to the dummy pedestal edge. Since the emitter is formed where the dummy pedestal existed, the extrinsic base is also self-aligned to the emitter. The silicon or polysilicon forming the inner extrinsic base extension region can also be grown in the trench with selective or non-selective epitaxy.

49. 发明授权

US06780695B1 BiCMOS integration scheme with raised extrinsic base 有权
标题翻译： BiCMOS整合方案具有突出的外在基础
公开(公告)号：US06780695B1
公开(公告)日：2004-08-24
申请号：US10249563
申请日：2003-04-18
申请人： Huajie Chen , Seshadri Subbanna , Basanth Jagannathan , Gregory G. Freeman , David C. Ahlgren , David Angell , Kathryn T. Schonenberg , Kenneth J. Stein , Fen F. Jamin
发明人： Huajie Chen , Seshadri Subbanna , Basanth Jagannathan , Gregory G. Freeman , David C. Ahlgren , David Angell , Kathryn T. Schonenberg , Kenneth J. Stein , Fen F. Jamin
IPC分类号： H01L218238
CPC分类号： H01L21/8249 , H01L27/0623
摘要： A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.
摘要翻译：提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。

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