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41. 发明授权

US08689158B2 System and method for performing static timing analysis in the presence of correlations between asserted arrival times 失效
标题翻译：在断言到达时间之间存在相关性的情况下执行静态时序分析的系统和方法
公开(公告)号：US08689158B2
公开(公告)日：2014-04-01
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译：一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。

42. 发明授权

US08423328B2 Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and mean 失效
标题翻译：使用统计学上正确的空间插值，随空间非均匀统计学相关性与距离，标准偏差和平均值分配随机变量的方法
公开(公告)号：US08423328B2
公开(公告)日：2013-04-16
申请号：US12570195
申请日：2009-09-30
申请人： John M. Cohn , Ulrich A. Finkler , David J. Hathaway , Jeffrey G. Hemmett , Fook-Luen Heng , Jason D Hibbeler , Gie Lee , Wayne H. Woods, Jr. , Cole E. Zemke
发明人： John M. Cohn , Ulrich A. Finkler , David J. Hathaway , Jeffrey G. Hemmett , Fook-Luen Heng , Jason D Hibbeler , Gie Lee , Wayne H. Woods, Jr. , Cole E. Zemke
IPC分类号： G06F17/17
CPC分类号： G06F17/175
摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.
摘要翻译：用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。

43. 发明申请

US20120311514A1 Decentralized Dynamically Scheduled Parallel Static Timing Analysis 失效
标题翻译：分散式动态调度并行静态时序分析
公开(公告)号：US20120311514A1
公开(公告)日：2012-12-06
申请号：US13150445
申请日：2011-06-01
申请人： Mark A. Lavin , David J. Hathaway , Kerim Kalafala , Jeffrey S. Piaget , Chandramouli Visweswariah
发明人： Mark A. Lavin , David J. Hathaway , Kerim Kalafala , Jeffrey S. Piaget , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes.
摘要翻译：一种用于执行并行静态时序分析的方法，其中多个进程独立地更新时序图，而不需要通过中央协调器模块进行通信。本地处理队列用于减少锁定开销，而不会导致过大的负载不平衡。对由多个互连节点形成的时序图表示的电路设计进行并行分析，该方法包括：使用计算机创建准备处理独立节点的共享工作队列; 将独立节点从工作队列分配到至少两个并行计算过程，同时执行其节点分析计算; 以及通过更新从所述节点分析获得的经处理的独立节点的值来修改所述电路设计，所述至少两个并行计算处理独立地更新所述共享工作队列以处理新的多个独立节点。

44. 发明授权

US08141014B2 System and method for common history pessimism relief during static timing analysis 有权
标题翻译：静态时序分析中共同历史悲观缓解的系统和方法
公开(公告)号：US08141014B2
公开(公告)日：2012-03-20
申请号：US12538229
申请日：2009-08-10
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Kerim Kalafala , Jeffrey P. Soreff
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.
摘要翻译：一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入对当前段的信号具有有界历史，至少一个传播和断言。该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

45. 发明申请

US20110077916A1 Method of Distributing a Random Variable Using Statistically Correct Spatial Interpolation Continuously With Spatially Inhomogeneous Statistical Correlation Versus Distance, Standard Deviation, and Mean 失效
标题翻译：使用统计学上正确的空间插值分布随机变量的方法与空间不均匀的统计相关性与距离，标准偏差和平均值
公开(公告)号：US20110077916A1
公开(公告)日：2011-03-31
申请号：US12570195
申请日：2009-09-30
申请人： John M Cohn , Ulrich A. Finkler , David J. Hathaway , Jefrey G. Hemmett , Fook-Luen Heng , Jason D. Hibbeler , Gie Lee , Wayne H. Woods, JR. , Cole E. Zemke
发明人： John M Cohn , Ulrich A. Finkler , David J. Hathaway , Jefrey G. Hemmett , Fook-Luen Heng , Jason D. Hibbeler , Gie Lee , Wayne H. Woods, JR. , Cole E. Zemke
IPC分类号： G06F17/10 , G06F17/17 , G06F1/02
CPC分类号： G06F17/175
摘要： Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.
摘要翻译：用空间不均匀的统计学相关性与距离，标准偏差和通过统计学校正的空间插值的平均值来建模随机变量的方法。该方法包括将统计独立的随机变量分配给坐标系中的一组种子点并在坐标系中的相应空间位置定义多个测试点。通过从分配给种子点的一个或多个随机变量的空间插值，为每个测试点确定随机变量的等式。该方法还包括利用相应的校正因子方程来调整每个测试点处的随机变量的方程。

46. 发明授权

US07870525B2 Slack sensitivity to parameter variation based timing analysis 有权
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07870525B2
公开(公告)日：2011-01-11
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

47. 发明申请

US20100180242A1 Method and system for efficient validation of clock skews during hierarchical static timing analysis 有权
标题翻译：在分层静态时序分析期间有效验证时钟偏差的方法和系统
公开(公告)号：US20100180242A1
公开(公告)日：2010-07-15
申请号：US12351944
申请日：2009-01-12
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Pooja M. Kotecha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method and a system for validating clock skews during a hierarchical static timing analysis of a chip or multi-chip package. Each pair of clock inputs of a hierarchical module bounds the allowable clock skew, creating new relative constraints on clock input arrival times propagated to those clock inputs. One embodiment is based on asserted arrival times and a maximum of computed slack values at said clock inputs, while a second embodiment is based on asserted arrival times and a minimum of downstream test slack values. The method further converts module clock assertions into a set of relative timing constraints to allow a hierarchical timing sign-off even in circumstances where absolute timing arrivals are not totally known at the time of module analysis.
摘要翻译：一种用于在芯片或多芯片封装的分层静态时序分析期间验证时钟偏移的方法和系统。分层模块的每对时钟输入限制了可允许的时钟偏移，从而在传播到这些时钟输入的时钟输入到达时间上产生新的相对约束。一个实施例基于确定的到达时间和在所述时钟输入处的计算的松弛值的最大值，而第二实施例基于确定的到达时间和最小的下游测试松弛值。该方法还将模块时钟断言转换成一组相对时序约束，以便即使在模块分析时绝对定时到达不是完全知道的情况下也允许分层定时签发。

48. 发明授权

US07716616B2 Slack sensitivity to parameter variation based timing analysis 失效
标题翻译：对基于参数变化的时序分析的松弛敏感性
公开(公告)号：US07716616B2
公开(公告)日：2010-05-11
申请号：US11930924
申请日：2007-10-31
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.
摘要翻译：公开了一种用于改进IC设计的方法，系统和程序产品，其优先考虑根据其故障概率导致校正的松弛故障系数。通过确定的一组独立参数，当参数变化时，通过注意时序上的差异，通常在端点松弛时，对每个参数执行灵敏度分析。对于每个独立参数重复此步骤。然后从参考松弛和每个定时端点的松弛的灵敏度计算失效系数，并且确定至少一个定时端点是否失败阈值测试。然后将失败的定时终点根据其故障系数进行优先级修改。所需的总运行次数是一次运行，用作参考运行，每个参数再运行一次运行。

49. 发明申请

US20090278222A1 INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE 有权
标题翻译：具有均匀多晶硅密度的集成电路，方法和设计结构
公开(公告)号：US20090278222A1
公开(公告)日：2009-11-12
申请号：US12117771
申请日：2008-05-09
申请人： Laura S. Chadwick , James A. Culp , David J. Hathaway , Anthony D. Polson
发明人： Laura S. Chadwick , James A. Culp , David J. Hathaway , Anthony D. Polson
IPC分类号： H01L27/00 , G06F17/50
CPC分类号： H01L27/0207 , G06F17/5072
摘要： Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.
摘要翻译：公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。这种重新配置以基本维持期望的去耦电容的方式执行。由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。

50. 发明申请

US20090276743A1 SYSTEM AND METHOD FOR COMPUTING PROXY SLACK DURING STATISTIC ANALYSIS OF DIGITAL INTEGRATED CIRCUITS 有权
标题翻译：数字集成电路统计分析中计算代码序列的系统与方法
公开(公告)号：US20090276743A1
公开(公告)日：2009-11-05
申请号：US12113288
申请日：2008-05-01
申请人： Joseph M. Frank , David J. Hathaway , Kerim Kalafala
发明人： Joseph M. Frank , David J. Hathaway , Kerim Kalafala
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zero if the late slack value is less than zero. Otherwise, if the late slack value is not less than zero, the method restricts the early proxy slack value to a maximum of the early slack value and the negative of the late slack value. To the contrary, for late mode timing analysis, the method sets a late proxy slack value to zero if the early slack value is less than zero. Otherwise, if the early proxy slack value is not less than zero, the method restricts the late proxy slack value to a maximum of the late slack value and the negative of the early slack value.
摘要翻译：使用代理松弛值在集成电路设计中优化信号定时的方法通过集成电路设计传播信号以输出定时信号。对于早期模式时序分析，如果迟滞值小于零，则该方法将早期代理松弛值设置为零。否则，如果迟到的值不小于零，则该方法将早期代理松弛值限制为早期松弛值的最大值和后期松弛值的负值。相反，对于晚期模式时序分析，如果早期松弛值小于零，则该方法将较晚的代理松弛值设置为零。否则，如果早期代理松弛值不小于零，则该方法将后期代理松弛值限制为最小的延迟松弛值，并将早期松弛值的负值限制。

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