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41. 发明授权

US06319770B1 Method for fabricating a bottom electrode of a dynamic random access memory capacitor 有权
标题翻译：一种用于制造动态随机存取存储器电容器的底部电极的方法
公开(公告)号：US06319770B1
公开(公告)日：2001-11-20
申请号：US09609265
申请日：2000-06-30
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L218242
CPC分类号： H01L28/87 , H01L27/10817 , H01L28/84
摘要： The present invention provides a method for fabricating a bottom electrode of a dynamic random access memory (DRAM) capacitor. First, a first sacrificial layer, an intermediate layer and a second sacrificial layer are sequentially formed on a substrate. Then, an aperture is formed on the first sacrificial layer, the intermediate layer and the second sacrificial layer. An annular groove is then formed in the inner circumferential surface of the aperture by removing a fixed depth of the intermediate layer. After that, the aperture and the annular groove are filled with a first amorphous silicon layer, a second amorphous silicon layer and a third amorphous silicon layer. The second amorphous silicon layer has a lower impurity concentration than those of the first amorphous silicon layer and the third amorphous silicon layer. The first amorphous silicon layer and the second amorphous silicon layer both fill into the annular groove and form an annular ring. Next, the first sacrificial layer and the second sacrificial layer are removed to reveal the first amorphous silicon layer. Next, a predetermined depth of the first amorphous silicon layer is removed to reveal the second amorphous silicon layer. Then, the intermediate layer is removed to reveal the first amorphous silicon layer at the annular ring. Finally, a plurality of hemispherical grains are formed on the first amorphous silicon layer and the second amorphous silicon layer.
摘要翻译：本发明提供一种用于制造动态随机存取存储器（DRAM）电容器的底部电极的方法。首先，在衬底上依次形成第一牺牲层，中间层和第二牺牲层。然后，在第一牺牲层，中间层和第二牺牲层上形成孔。然后通过去除中间层的固定深度，在孔的内周表面中形成环形槽。之后，孔和环形槽填充有第一非晶硅层，第二非晶硅层和第三非晶硅层。第二非晶硅层的杂质浓度比第一非晶硅层和第三非晶硅层的杂质浓度低。第一非晶硅层和第二非晶硅层都填充到环形槽中并形成环形环。接下来，去除第一牺牲层和第二牺牲层以露出第一非晶硅层。接下来，去除第一非晶硅层的预定深度以露出第二非晶硅层。然后，去除中间层以在环形环处露出第一非晶硅层。最后，在第一非晶硅层和第二非晶硅层上形成多个半球状晶粒。

42. 发明授权

US06274497B1 Copper damascene manufacturing process 有权
标题翻译：铜大马士革制造工艺
公开(公告)号：US06274497B1
公开(公告)日：2001-08-14
申请号：US09499067
申请日：2000-02-04
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L2144
CPC分类号： H01L21/76844 , H01L21/76802 , H01L21/76874 , H01L21/76879 , H01L21/76886
摘要： A copper damascene process for forming copper plugs. A conductive structure that includes an amorphous silicon layer and a metal line is formed over a substrate. A dielectric liner layer is formed over the conductive structure and the substrate. A multi-level dielectric layer is formed over the dielectric liner layer, then the multi-level dielectric layer and dielectric liner layer are patterned to form a via that exposes a portion of the amorphous silicon layer on the conductive line. Metal barrier spacers are formed on the sidewalls of the via. A copper displacement process is next carried out to convert the amorphous silicon layer into a first copper layer. Since a portion of the metal barrier spacers is also converted into a second copper layer. a process is carried out to remove the second copper layer from the metal barrier spacers. Using the first copper layer as a seeding layer, a copper electroless plating is carried out. Copper is accumulated from the bottom of the via anisotropically so that a copper plug is ultimately formed inside the via.
摘要翻译：用于形成铜插头的铜镶嵌工艺。在衬底上形成包括非晶硅层和金属线的导电结构。介电衬里层形成在导电结构和衬底之上。在电介质衬垫层之上形成多层电介质层，然后对多层电介质层和电介质衬层进行构图以形成通孔，该通孔暴露导电线上的非晶硅层的一部分。在通孔的侧壁上形成金属阻挡隔离物。接下来进行铜位移处理以将非晶硅层转化为第一铜层。由于金属阻挡隔离物的一部分也转变成第二铜层。进行从金属屏障间隔物除去第二铜层的工序。使用第一铜层作为接种层，进行铜无电镀。铜从各向异性的底部堆积，从而最终在通孔内形成铜塞。

43. 发明授权

US06271116B1 Method of fabricating interconnects 有权
标题翻译：制造互连的方法
公开(公告)号：US06271116B1
公开(公告)日：2001-08-07
申请号：US09528645
申请日：2000-03-20
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76831 , H01L21/76835
摘要： A method for fabricating interconnects is described. A semiconductor substrate having metal lines is provided. A liner layer is formed over the substrate, and then a dielectric layer is formed between the metal lines, wherein the dielectric layer has a low dielectric constant. Patterned thermal conductivity layers are formed surrounding the predetermined regions of vias. Thereafter, another dielectric layer with low dielectric constant is formed between the patterned thermal conductivity layers, and then a planar cap layer is formed over the substrate. Via openings exposing the metal lines are formed in the planar cap layer, the patterned thermal conductivity layer and the liner layer. A metal material is filled in the via openings to form vias.
摘要翻译：描述了制造互连的方法。提供具有金属线的半导体衬底。在衬底上形成衬层，然后在金属线之间形成介电层，其中介电层具有低的介电常数。在通孔的预定区域周围形成图案化的导热层。此后，在图案化导热层之间形成具有低介电常数的另一介质层，然后在衬底上形成平面覆盖层。在平面盖层，图案化导热层和衬里层中形成暴露金属线的通孔。金属材料填充在通路孔中以形成通孔。

44. 发明授权

US06271099B1 Method for forming a capacitor of a DRAM cell 有权
标题翻译：用于形成DRAM单元的电容器的方法
公开(公告)号：US06271099B1
公开(公告)日：2001-08-07
申请号：US09406728
申请日：1999-09-28
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L2120
CPC分类号： H01L27/10855 , H01L28/91
摘要： A method for forming a DRAM cell with a crown full metal capacitor electrode with integrated selective tungsten contact hole. When the MOSFET devices are defined, a metal landing pad with Ti/TiN/W/TiN is first deposited and etched. After an insulating layer is deposited and node contact is formed, a CVD TiN layer is deposited and etched to form TiN spacers on the node contact sidewalls. Next, selective tungsten is formed in the node contact and use reactive ion etching to etch back. Thereafter, another insulating layer is deposited and the crown pattern opening is formed. Then, a TiN/W metal layer is deposited to serve as the bottom electrode of the stacked capacitor. After a photoresist layer is formed, then a chemical mechanical polishing method is used to remove portions of the photoresist layer and the TiN/W metal layer by using insulating layer as an polishing stop. The remaining photoresist and insulating layer are removed. Subsequently, a high dielectric film and another metal layer is deposited to complete the present invention. The process of the invention to fill the high aspect ratio node contact with selective tungsten and the stacked capacitor with metal electrode structure will provide a high reliability DRAM cell.
摘要翻译：一种用具有集成的选择性钨接触孔的表冠全金属电容器电极形成DRAM单元的方法。当限定MOSFET器件时，首先沉积具有Ti / TiN / W / TiN的金属着陆焊盘并进行蚀刻。在沉积绝缘层并形成节点接触之后，沉积并蚀刻CVD TiN层以在节点接触侧壁上形成TiN间隔物。接下来，在节点接触中形成选择性钨，并使用反应离子蚀刻来回蚀刻。此后，沉积另一绝缘层，形成表冠图形开口。然后，沉积TiN / W金属层以用作层叠电容器的底部电极。在形成光致抗蚀剂层之后，使用化学机械抛光方法通过使用绝缘层作为抛光停止来去除部分光致抗蚀剂层和TiN / W金属层。去除剩余的光致抗蚀剂和绝缘层。随后，沉积高电介质膜和另一金属层以完成本发明。本发明填充与选择性钨的高纵横比节点接触和具有金属电极结构的堆叠电容器的过程将提供高可靠性DRAM单元。

45. 发明授权

US06211569B1 Interconnection lines for improving thermal conductivity in integrated circuits and method for fabricating the same 有权
标题翻译：用于提高集成电路中的导热性的互连线及其制造方法
公开(公告)号：US06211569B1
公开(公告)日：2001-04-03
申请号：US09400626
申请日：1999-09-20
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L2348
CPC分类号： H01L23/522 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a structure of metal interconnection lines in integrated circuits for improving thermal conductivity therein. In the structure, a silicon nitride layer is formed underneath a first metal pattern of integrated circuits. Moreover, a silicon nitride plug is formed between two adjacent metal patterns and it serves as a thermal conductor. At least one metal plug in dielectric layers between the metal patterns is an electrical connection of integrated circuits. The present invention also discloses a method for fabricating the structure as mentioned above.
摘要翻译：本发明公开了一种用于提高其导热性的集成电路中的金属互连线的结构。在该结构中，在集成电路的第一金属图案之下形成氮化硅层。此外，在两个相邻的金属图案之间形成氮化硅塞，并且其用作导热体。金属图案之间的电介质层中的至少一个金属插塞是集成电路的电连接。本发明还公开了如上所述的用于制造结构的方法。

46. 发明授权

US06187486B1 Method of multi-exposure for improving photolithography resolution 有权
标题翻译：用于提高光刻分辨率的多曝光方法
公开(公告)号：US06187486B1
公开(公告)日：2001-02-13
申请号：US09250766
申请日：1999-02-16
申请人： Jun-Cheng Lai , Yeur-Luen Tu , Chine-Gie Lou
发明人： Jun-Cheng Lai , Yeur-Luen Tu , Chine-Gie Lou
IPC分类号： G03F900
CPC分类号： G03F7/70466 , G03F7/2022 , G03F7/203
摘要： A multi-exposure process. By performing the multi-exposure process, the size of the line width can be enlarged or shrunk by the precondition of the fixed pitch. Moreover, the line width can be shrunk to a level even smaller than the resolving power of the stepper or the scanner. Additionally, by using the invention, the exposure energy, the exposure time and the exposure DOF can be fixed while the exposure process is performed. Therefore, the process window is increased and the yield is enhanced. Furthermore, the processing sequence according to the invention is simpler than the conventional photolithography processing sequence, so that the throughput can be increased.
摘要翻译：多曝光过程。通过进行多次曝光处理，可以通过固定间距的前提来扩大或缩小线宽的尺寸。此外，线宽可以缩小到甚至小于步进器或扫描仪的分辨率的水平。此外，通过使用本发明，可以在执行曝光处理时固定曝光能量，曝光时间和曝光DOF。因此，处理窗口增加，产量提高。此外，根据本发明的处理顺序比常规的光刻处理顺序更简单，从而可以提高吞吐量。

47. 发明授权

US06177308B1 Method for manufacturing stacked capacitor 有权
标题翻译：叠层电容器的制造方法
公开(公告)号：US06177308B1
公开(公告)日：2001-01-23
申请号：US09299963
申请日：1999-04-26
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/84
摘要： A method for stacked capacitor. The method utilizes a silicon nitride layer as an etching stop layer for removing the insulation layer on each side of a crown-shaped capacitor structure. As soon as the insulation layer is removed the silicon nitride layer is removed as well. In addition, a high-temperature oxide layer is formed over the inter-layer dielectric. The high-temperature oxide layer can prevent the formation of hemispherical grains on its surface when selective hemispherical grains are formed on the surface of an amorphous silicon layer.
摘要翻译：一种叠层电容器的方法。该方法利用氮化硅层作为蚀刻停止层，用于去除冠形电容器结构的每一侧的绝缘层。一旦绝缘层被去除，氮化硅层也被去除。此外，在层间电介质上形成高温氧化物层。当在非晶硅层的表面上形成选择性半球状晶粒时，高温氧化物层可以防止其表面上的半球状晶粒的形成。

48. 发明授权

US06171956B2 Method for improving the thermal conductivity of metal lines in integrated circuits 有权
标题翻译：提高集成电路中金属线路导热率的方法
公开(公告)号：US06171956B2
公开(公告)日：2001-01-09
申请号：US09391496
申请日：1999-09-08
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L2144
CPC分类号： H01L28/92 , C23F4/00 , H01L21/76801 , H01L21/76885 , H01L23/5283 , H01L2924/0002 , H01L2924/12044 , Y10S148/105 , Y10S148/106 , Y10S438/964 , H01L2924/00
摘要： The method includes forming a metal layer over a substrate. Subsequently, a discrete dot masking is deposited on the surface of the metal layer. A discrete rugged polysilicon or hemispherical grained silicon (HSG-Si) can be chosen as the discrete dot masking. The source gas used to form the discrete rugged polysilicon includes Si2H6 at a temperature of about 400 to 450° C. An anisotropically etching step is performed to etch the metal layer by using the discrete dot masking as an etching mask, thereby forming a surface pattern formed thereon. Then, the discrete dot masking is removed. The metal layer is patterned to a conductive line pattern. An organic material layer with low dielectric constant is formed on the patterned metal layer. A silicon oxide layer is successively formed on the organic material layer, followed by polishing the silicon oxide layer using a chemical mechanical polishing (CMP).
摘要翻译：该方法包括在衬底上形成金属层。随后，离散的点掩模沉积在金属层的表面上。可以选择离散的坚固多晶硅或半球状晶粒硅（HSG-Si）作为离散点掩模。用于形成离散坚固多晶硅的源气体包括在约400至450℃的温度下的Si 2 H 6。通过使用离散点掩模作为蚀刻掩模来进行各向异性蚀刻步骤以蚀刻金属层，从而形成表面图案形成在其上。然后，去除离散点掩蔽。将金属层图案化为导电线图案。在图案化的金属层上形成具有低介电常数的有机材料层。在有机材料层上依次形成氧化硅层，然后使用化学机械研磨（CMP）研磨氧化硅层。

49. 发明授权

US6143605A Method for making a DRAM capacitor using a double layer of insitu doped polysilicon and undoped amorphous polysilicon with HSG polysilicon 失效
标题翻译：使用双层掺杂多晶硅和未掺杂的无定形多晶硅制造DRAM电容器的方法
公开(公告)号：US6143605A
公开(公告)日：2000-11-07
申请号：US41863
申请日：1998-03-12
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/84
摘要： A method of making a capacitor over a contact. The method comprises the steps of: (a) depositing an oxide layer over said contact; (b) forming a dual damascene opening in said oxide layer over said contact; (c) depositing a layer of insitu doped polysilicon over said dual damascene opening and said oxide layer; (d) depositing a layer of undoped amorphous polysilicon over said layer of insitu doped polysilicon; (e) removing said layer of undoped amorphous polysilicon and said layer of insitu doped polysilicon that is outside of said dual damascene opening; (f) removing said oxide layer to leave a dual damascene structure comprising insitu doped polysilicon and undoped amorphous polysilicon; (g) forming hemispherical grain (HSG) polysilicon on the surface of said dual damascene structure; (h) forming a dielectric layer over said dual damascene structure; and (i) forming a top electrode over said dielectric layer.
摘要翻译：在触点上制作电容器的方法。该方法包括以下步骤：（a）在所述触点上沉积氧化物层; （b）在所述触点上形成所述氧化物层中的双镶嵌开口; （c）在所述双镶嵌开口和所述氧化物层上沉积一层原位掺杂多晶硅; （d）在所述本征掺杂多晶硅层上沉积未掺杂的非晶多晶硅层; （e）去除在所述双镶嵌开口之外的所述非掺杂非晶多晶硅层和所述本征掺杂多晶硅层; （f）去除所述氧化物层以留下包括原位掺杂多晶硅和未掺杂的非晶多晶硅的双镶嵌结构; （g）在所述双镶嵌结构的表面上形成半球形晶粒（HSG）多晶硅; （h）在所述双镶嵌结构上形成电介质层; 和（i）在所述介电层上形成顶部电极。

50. 发明授权

US6117748A Dishing free process for shallow trench isolation 失效
标题翻译：用于浅沟槽隔离的免洗工艺
公开(公告)号：US6117748A
公开(公告)日：2000-09-12
申请号：US60771
申请日：1998-04-15
申请人： Chine-Gie Lou , Yeur-Luen Tu , Ko-Hsing Chang
发明人： Chine-Gie Lou , Yeur-Luen Tu , Ko-Hsing Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A thin silicon dioxide layer is formed on a substrate to act as a pad oxide layer. Subsequently, a Si.sub.3 N.sub.4 or BN layer is deposited on the pad oxide layer. An in situ doped polysilicon layer is deposited on the Si.sub.3 N.sub.4 or BN layer. A trench is formed in the substrate. An oxide liner is formed along the walls of the trench and on the surface of the in situ doped polysilicon layer. A CVD oxide layer is formed on the oxide liner and refilled into the trench. A two-step chemical mechanical polishing (CMP) removes the layers to the surface of the Si.sub.3 N.sub.4 or BN layer. The first step of the two-step CMP is an oxide slurry CMP that is stopped at about 100 to 500 angstroms from the in situ doped polysilicon layer. The second step of the two-step CMP is a poly slurry CMP that is controlled to stop at the surface of the Si.sub.3 N.sub.4 or BN layer.
摘要翻译：在基板上形成薄的二氧化硅层，作为衬垫氧化物层。随后，在衬垫氧化物层上沉积Si 3 N 4或BN层。在Si 3 N 4或BN层上沉积原位掺杂多晶硅层。在衬底中形成沟槽。沿着沟槽的壁和原位掺杂的多晶硅层的表面上形成氧化物衬垫。在氧化物衬垫上形成CVD氧化层，并重新填充到沟槽中。两步化学机械抛光（CMP）去除层到Si3N4或BN层的表面。两步CMP的第一步是从原位掺杂的多晶硅层停止在约100至500埃处的氧化物浆料CMP。两步CMP的第二步是控制在Si3N4或BN层表面停止的聚浆料CMP。

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