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41. 发明授权

US06897131B2 Advances in spike anneal processes for ultra shallow junctions 失效
标题翻译：超浅结点尖峰退火工艺的进展
公开(公告)号：US06897131B2
公开(公告)日：2005-05-24
申请号：US10668682
申请日：2003-09-22
申请人： Balasubramanian Ramachandran , Ravi Jallepally , Ryan C. Boas , Sundar Ramamurthy , Amir Al-Bayati , Houda Graoui , Joseph M. Spear
发明人： Balasubramanian Ramachandran , Ravi Jallepally , Ryan C. Boas , Sundar Ramamurthy , Amir Al-Bayati , Houda Graoui , Joseph M. Spear
IPC分类号： H01L21/00 , H01L21/265 , H01L21/268 , H01L21/324 , H01L21/425
CPC分类号： H01L21/324 , H01L21/26513 , H01L21/2686 , H01L21/67109 , H01L21/67115
摘要： Lamp based spike annealing was improved to address the aggressive requirements of
摘要翻译：改进了基于灯的尖峰退火以满足<100nm超浅结点（USJ）技术的积极要求。改进的重点是提高冷却速率，从而提高尖峰锐度。然后将具有不同离子注入能量和剂量的硼离子注入衬底退火以表征尖峰退火的改进。在具有改进的尖峰轮廓退火的基底上实现了薄膜电阻和结深度的大于10％的改善。改进的尖峰退火具有与标准尖峰退火相同的可比均匀性。

42. 发明授权

US08900405B2 Plasma immersion ion implantation reactor with extended cathode process ring 有权
标题翻译：具有扩展阴极工艺环的等离子体浸没离子注入反应器
公开(公告)号：US08900405B2
公开(公告)日：2014-12-02
申请号：US11985579
申请日：2007-11-14
申请人： Peter I. Porshnev , Majeed A. Foad , Kartik Ramaswamy , Biagio Gallo , Hiroji Hanawa , Andrew Nguyen , Kenneth S. Collins , Amir Al-Bayati
发明人： Peter I. Porshnev , Majeed A. Foad , Kartik Ramaswamy , Biagio Gallo , Hiroji Hanawa , Andrew Nguyen , Kenneth S. Collins , Amir Al-Bayati
IPC分类号： C23C16/00 , H01L21/306 , H01J37/32
CPC分类号： H01J37/32642 , H01J37/32412
摘要： The disclosure concerns a process ring for the wafer support pedestal of a toroidal source plasma immersion ion implantation reactor. The process ring improves edge uniformity by providing a continuous surface extending beyond the wafer edge, in one embodiment. In another embodiment, the process ring includes a floating electrode that functions as an extension of the wafer support electrode by RF coupling at the bias frequency.
摘要翻译：本公开涉及用于环形源等离子体浸入式离子注入反应器的晶片支撑基座的工艺环。在一个实施例中，处理环通过提供延伸超过晶片边缘的连续表面来提高边缘均匀性。在另一个实施例中，处理环包括浮动电极，其通过在偏置频率下的RF耦合用作晶片支撑电极的延伸。

43. 发明申请

US20130242287A1 Process and Apparatus for Measuring the Crystal Fraction of Crystalline Silicon Casted Mono Wafers 有权
标题翻译：用于测量晶体硅铸造单晶硅晶体分数的方法和装置
公开(公告)号：US20130242287A1
公开(公告)日：2013-09-19
申请号：US13421194
申请日：2012-03-15
申请人： Asaf Schlezinger , Amir Al-Bayati
发明人： Asaf Schlezinger , Amir Al-Bayati
IPC分类号： G01N21/59 , G01N21/55
CPC分类号： G01N21/59
摘要： Provided are methods and apparatus for determining the crystal fraction of a casted-mono silicon wafer. A light source is directed at the wafer and the transmission or reflection is measured by a detector. An image of the wafer is generated by a processor and the crystal fraction is calculated from the generated image. The crystal fraction is correlated to the efficiency of the solar cell produced, allowing for the rejection of inferior wafers prior to processing.
摘要翻译：提供了用于确定铸造单晶硅晶片的晶体分数的方法和装置。光源指向晶片，透射或反射由检测器测量。由处理器生成晶片的图像，并根据所生成的图像计算晶体分数。晶体分数与所制造的太阳能电池的效率相关，允许在处理之前排出劣质晶片。

44. 发明授权

US08501568B2 Method of forming flash memory with ultraviolet treatment 失效
标题翻译：用紫外线处理形成闪存的方法
公开(公告)号：US08501568B2
公开(公告)日：2013-08-06
申请号：US12256173
申请日：2008-10-22
申请人： Mihaela Balseanu , Vladimir Zubkov , Li-Qun Xia , Atif Noori , Reza Arghavani , Derek R. Witty , Amir Al-Bayati
发明人： Mihaela Balseanu , Vladimir Zubkov , Li-Qun Xia , Atif Noori , Reza Arghavani , Derek R. Witty , Amir Al-Bayati
IPC分类号： H01L21/326 , H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L21/00 , H01L29/792
CPC分类号： H01L21/3185 , H01L21/28282 , H01L21/3105 , H01L21/3115 , H01L21/31155 , H01L29/42332 , H01L29/7881 , H01L29/792
摘要： A methods of forming a flash memory device are provided. The flash memory device comprises a silicon dioxide layer on a substrate and a silicon nitride layer that is formed on the silicon dioxide layer. The properties of the silicon nitride layer can be modified by any of: exposing the silicon nitride layer to ultraviolet radiation, exposing the silicon nitride layer to an electron beam, and by plasma treating the silicon nitride layer. A dielectric material is deposited on the silicon nitride layer and a conductive date is formed over the dielectric material. The flash memory device with modified silicon nitride layer provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
摘要翻译：提供了形成闪速存储器件的方法。闪存器件包括在衬底上的二氧化硅层和形成在二氧化硅层上的氮化硅层。氮化硅层的性质可以通过以下任何方式改变：将氮化硅层暴露于紫外线辐射，将氮化硅层暴露于电子束，以及通过等离子体处理氮化硅层。介电材料沉积在氮化硅层上，并且在电介质材料上形成导电日期。具有改进的氮化硅层的闪速存储器件提供了非易失性存储器件的单元电池的电荷保持容量和电荷保持时间的增加。

45. 发明申请

US20130008878A1 THERMAL FLUX ANNEALING INFLUENCE OF BURIED SPECIES 有权
标题翻译： ED ED。。。。。。。。。。。。。。。。。。
公开(公告)号：US20130008878A1
公开(公告)日：2013-01-10
申请号：US13619898
申请日：2012-09-14
申请人： Dean C. Jennings , Amir Al-Bayati
发明人： Dean C. Jennings , Amir Al-Bayati
IPC分类号： B23K26/00
CPC分类号： H01L21/268 , B23K26/0738 , H01L21/26533 , H01L21/324
摘要： A method including introducing a species into a substrate including semiconductor material; and translating linearly focused electromagnetic radiation across a surface of the substrate, the electromagnetic radiation being sufficient to thermally influence the species. An apparatus including an electromagnetic radiation source; a stage having dimensions suitable for accommodating a semiconductor substrate within a chamber; an optical element disposed between the electromagnetic radiation source and the stage to focus radiation from the electromagnetic radiation source into a line having a length determined by the diameter of a substrate to be placed on the stage; and a controller coupled to the electromagnetic radiation source including machine readable program instructions that allow the controller to control the depth into which a substrate is exposed to the radiation.
摘要翻译：一种方法，包括将物质引入到包括半导体材料的基板中; 并且将线性聚焦的电磁辐射平移在衬底的表面上，电磁辐射足以热影响物质。一种包括电磁辐射源的设备; 具有适于容纳半导体衬底在腔室内的尺寸的平台; 设置在所述电磁辐射源和所述台之间的光学元件，用于将来自所述电磁辐射源的辐射聚焦成具有由要放置在所述台上的基板的直径确定的长度的线; 以及耦合到电磁辐射源的控制器，包括允许控制器控制衬底暴露于辐射的深度的机器可读程序指令。

46. 发明申请

US20100096687A1 NON-VOLATILE MEMORY HAVING SILICON NITRIDE CHARGE TRAP LAYER 有权
标题翻译：非易失性存储器，含有硝酸盐电荷捕获层
公开(公告)号：US20100096687A1
公开(公告)日：2010-04-22
申请号：US12255617
申请日：2008-10-21
申请人： Mihaela BALSEANU , Vladimir Zubkov , Li-Qun Xia , Atif Noori , Reza Arghavani , Derek R. Witty , Amir Al-Bayati
发明人： Mihaela BALSEANU , Vladimir Zubkov , Li-Qun Xia , Atif Noori , Reza Arghavani , Derek R. Witty , Amir Al-Bayati
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/31
CPC分类号： H01L21/3185 , H01L21/28282 , H01L21/3105 , H01L21/3115 , H01L21/31155 , H01L29/42332 , H01L29/7881 , H01L29/792
摘要： A flash memory device and methods of forming a flash memory device are provided. The flash memory device includes a doped silicon nitride layer having a dopant comprising carbon, boron or oxygen. The doped silicon nitride layer generates a higher number and higher concentration of nitrogen and silicon dangling bonds in the layer and provides an increase in charge holding capacity and charge retention time of the unit cell of a non-volatile memory device.
摘要翻译：提供闪速存储器件和形成闪存器件的方法。闪速存储器件包括具有包含碳，硼或氧的掺杂剂的掺杂氮化硅层。掺杂的氮化硅层在该层中产生更高数量和更高浓度的氮和硅悬挂键，并且提供了非易失性存储器件的单元电池的电荷保持容量和电荷保留时间的增加。

47. 发明授权

US07566655B2 Integration process for fabricating stressed transistor structure 有权
标题翻译：用于制造应力晶体管结构的集成工艺
公开(公告)号：US07566655B2
公开(公告)日：2009-07-28
申请号：US11398436
申请日：2006-04-05
申请人： Mihaela Balseanu , Jia Lee , Mei-Yee Shek , Amir Al-Bayati , Li-Qun Xia , Hichem M'Saad
发明人： Mihaela Balseanu , Jia Lee , Mei-Yee Shek , Amir Al-Bayati , Li-Qun Xia , Hichem M'Saad
IPC分类号： H01L21/44
CPC分类号： H01L29/7843 , C23C16/345 , C23C16/56 , H01L21/28044 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/4925 , H01L29/66545 , H01L29/66583
摘要： A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.
摘要翻译：工艺流程集成方案采用一种或多种技术来控制由此形成的半导体器件中的应力。根据一个实施例，由氮化物间隔物和多晶硅栅极的RTP贡献的累积应力以及随后沉积高应力蚀刻停止层，增强应变并提高器件性能。可以将锗沉积或植入栅极结构中以便于应力控制。

48. 发明申请

US20090120367A1 Plasma immersion ion implantation reactor with extended cathode process ring 有权
标题翻译：具有扩展阴极工艺环的等离子体浸没离子注入反应器
公开(公告)号：US20090120367A1
公开(公告)日：2009-05-14
申请号：US11985579
申请日：2007-11-14
申请人： Peter I. Porshnev , Majeed A. Foad , Kartik Ramaswamy , Biagio Gallo , Hiroji Hanawa , Andrew Nguyen , Kenneth S. Collins , Amir Al-Bayati
发明人： Peter I. Porshnev , Majeed A. Foad , Kartik Ramaswamy , Biagio Gallo , Hiroji Hanawa , Andrew Nguyen , Kenneth S. Collins , Amir Al-Bayati
IPC分类号： C23C16/513
CPC分类号： H01J37/32642 , H01J37/32412
摘要： The disclosure concerns a process ring for the wafer support pedestal of a toroidal source plasma immersion ion implantation reactor. The process ring improves edge uniformity by providing a continuous surface extending beyond the wafer edge, in one embodiment. In another embodiment, the process ring includes a floating electrode that functions as an extension of the wafer support electrode by RF coupling at the bias frequency.
摘要翻译：本公开涉及用于环形源等离子体浸入式离子注入反应器的晶片支撑基座的工艺环。在一个实施例中，处理环通过提供延伸超过晶片边缘的连续表面来提高边缘均匀性。在另一个实施例中，处理环包括浮动电极，其通过在偏置频率下的RF耦合用作晶片支撑电极的延伸。

49. 发明申请

US20090093112A1 METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY 有权
标题翻译：用于减少RC延迟的电介质层中产生气泡的方法和装置
公开(公告)号：US20090093112A1
公开(公告)日：2009-04-09
申请号：US11869396
申请日：2007-10-09
申请人： AMIR AL-BAYATI , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang 'David' Cui , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Li-Qun Xia
发明人： AMIR AL-BAYATI , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang 'David' Cui , Mihaela Balseanu , Meiyee (Maggie Le) Shek , Li-Qun Xia
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/3105 , H01L21/31111 , H01L21/31144 , H01L21/76825 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
摘要翻译：一种用于在互连结构的电介质材料中产生气隙的方法和装置。一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层，在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。

50. 发明申请

US20080254233A1 PLASMA-INDUCED CHARGE DAMAGE CONTROL FOR PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION PROCESSES 审中-公开
标题翻译：用于等离子体增强化学蒸气沉积过程的等离子体诱导电荷损失控制
公开(公告)号：US20080254233A1
公开(公告)日：2008-10-16
申请号：US11733531
申请日：2007-04-10
申请人： KWANGDUK DOUGLAS LEE , Matthew Spuller , Martin Jay Seamons , Wendy H. Yeh , Bok Hoen Kim , Mohamad Ayoub , Amir Al-Bayati , Derek R. Witty , Hichem M'Saad
发明人： KWANGDUK DOUGLAS LEE , Matthew Spuller , Martin Jay Seamons , Wendy H. Yeh , Bok Hoen Kim , Mohamad Ayoub , Amir Al-Bayati , Derek R. Witty , Hichem M'Saad
IPC分类号： C23C14/28
CPC分类号： C23C16/26 , C23C16/52
摘要： Methods of depositing amorphous carbon films on substrates are provided herein. The methods reduce or prevent plasma-induced charge damage to the substrates from the deposition of the amorphous carbon films. In one aspect, an initiation layer of amorphous carbon is deposited at a low RF power level and/or at a low hydrocarbon compound/inert gas flow rate ratio before a bulk layer of amorphous carbon is deposited. After the deposition of the initiation layer, the RF power, hydrocarbon flow rate, and inert gas flow rate may be ramped to final values for the deposition of the bulk layer, wherein the RF power ramp rate is typically greater than the ramp rates of the hydrocarbon compound and of the inert gas. In another aspect, a method of minimizing plasma-induced charge damage includes depositing a seasoning layer on one or more interior surfaces of a chamber before the deposition of the amorphous carbon film on a substrate therein or coating the interior surfaces with an oxide or dielectric layer during manufacturing.
摘要翻译：本文提供了在基片上沉积非晶碳膜的方法。该方法从无定形碳膜的沉积中减少或防止等离子体对基板的电荷损伤。在一个方面，在堆积无定形碳沉积层之前，以低RF功率水平和/或低烃化合物/惰性气体流速比沉积无定形碳的起始层。在起始层的沉积之后，RF功率，烃流速和惰性气体流速可以斜坡化到用于沉积体层的最终值，其中RF功率斜坡率通常大于烃化合物和惰性气体。在另一方面，一种使等离子体感应的电荷损伤最小化的方法包括在将非晶碳膜沉积在基底上之前，在腔室的一个或多个内表面上沉积调味层，或者用氧化物或介电层涂覆内表面在制造过程中。

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