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31. 发明授权

US4924484A High speed digital counter 失效
标题翻译：高速数字计数器
公开(公告)号：US4924484A
公开(公告)日：1990-05-08
申请号：US263092
申请日：1988-10-27
申请人： Lawrence J. Grasso , Dale E. Hoffman , Carroll E. Morgan , Charles A. Puntar , Diane K. Young
发明人： Lawrence J. Grasso , Dale E. Hoffman , Carroll E. Morgan , Charles A. Puntar , Diane K. Young
IPC分类号： H03K23/00 , H03K3/037 , H03K23/40 , H03K23/50
CPC分类号： H03K3/0372 , H03K23/50
摘要： A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.

32. 发明授权

US4912734A High resolution event occurrance time counter 失效
标题翻译：高分辨率事件发生时间计数器
公开(公告)号：US4912734A
公开(公告)日：1990-03-27
申请号：US310766
申请日：1989-02-14
申请人： Richard M. Frauenglass
发明人： Richard M. Frauenglass
IPC分类号： G04F10/04 , H03K21/40 , H03K23/40 , H03K23/54
CPC分类号： G04F10/04 , H03K21/40 , H03K23/40 , H03K23/542
摘要： A high resolution event occurrence time counter includes a free running counter which is responsive to a clock signal and which provides count data that varies in response to the clock signal. A first register stores the count data of the free running counter. The first register provides first register data representative of the count data stored in the register. A second register stores the first register data and provides first time of arrival data representative of the first register data stored in the second register. A third register stores the count data of the free running counter. The third register provides second time of arrival data representative of the count data which is stored in the third register. A clock edge encoder determines whether an event occurred during the first half cycle of the clock signal or during the second half cycle. The clock edge encoder provides a first sync signal when the event occurred during the first half cycle, and a second sync signal when the event occurred during the second half cycle. The second register stores the first register data in response to the first sync signal, and the third register stores the count data in response to the second sync signal. Either the first time of arrival data or the second time of arrival data, depending on whether the first or second sync signal is generated, is provided as output time of arrival data of the event occurrence time counter.
摘要翻译：高分辨率事件发生时间计数器包括响应于时钟信号的自由运行计数器，并且提供响应于时钟信号而变化的计数数据。第一个寄存器存储自由运行计数器的计数数据。第一个寄存器提供表示存储在寄存器中的计数数据的第一寄存器数据。第二寄存器存储第一寄存器数据，并且提供表示存储在第二寄存器中的第一寄存器数据的第一到达数据。第三个寄存器存储自由运行计数器的计数数据。第三寄存器提供代表存储在第三寄存器中的计数数据的第二次到达数据。时钟边沿编码器确定在时钟信号的前半周期期间或在第二个半周期期间是否发生事件。时钟沿编码器在前半个周期内发生事件时提供第一同步信号，而在第二个半周期期间发生事件时提供第二同步信号。第二寄存器响应于第一同步信号存储第一寄存器数据，并且第三寄存器响应于第二同步信号存储计数数据。作为事件发生时间计数器的到达数据的输出时间，提供第一次到达数据或第二次到达数据，取决于是否产生第一或第二同步信号。

33. 发明授权

US4759043A CMOS binary counter 失效
标题翻译： CMOS二进制计数器
公开(公告)号：US4759043A
公开(公告)日：1988-07-19
申请号：US33381
申请日：1987-04-02
申请人： Edward T. Lewis
发明人： Edward T. Lewis
IPC分类号： H03K23/00 , H03K3/356 , H03K21/17 , H03K23/40 , H03K23/50 , H03K23/52 , H03K23/44
CPC分类号： H03K3/356104 , H03K21/17 , H03K23/52
摘要： A 1.2 .mu.m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic "zero" state. Once the count enable is raised to the logic "one" state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a "zero" state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.
摘要翻译：具有200MHz时钟速率的1.2μmCMOS二进制计数器包括可以连接在多个4位部分中的4位计数部分。 4位计数器部分中的每个位级都使用这种级的当前状态来确定在下一级中发生了什么。每个4位部分通过添加最低阶进位位输入的连续处理来执行计数功能。计数使能信号用于启用计数过程以及用作到第一级的进位位输入。当处于逻辑“零”状态时，计数使能会影响计数器复位。一旦计数使能提高到逻辑“1”状态，计数过程就从第一个时钟脉冲的上升沿开始。只要保持计数使能，继续计数。当计数使能降低到“零”状态时，计数结束，计数器复位发生在时钟的下一个顺序上升沿。

34. 发明授权

US4758737A Clock generator circuit 失效
标题翻译：时钟发生器电路
公开(公告)号：US4758737A
公开(公告)日：1988-07-19
申请号：US85818
申请日：1987-07-20
申请人： Takaaki Hirano
发明人： Takaaki Hirano
IPC分类号： H03K21/40 , G01R31/28 , H03K5/00 , H03K5/135 , H03K23/00 , H03K23/40 , H03K5/13 , H03K1/17
CPC分类号： H03K5/135
摘要： A clock generator circuit of this invention is for an integrated circuit which is controlled by clock signals obtained by frequency-dividing a standard clock. Three flip-flops, two of which are connected in series, and two logical gates together form a synchronization circuit such that when a command signal is inputted to start testing the integrated circuit, frequency-divided clock signals in synchronism with a standard clock are outputted.
摘要翻译：本发明的时钟发生器电路用于由通过对标准时钟进行分频而获得的时钟信号控制的集成电路。三个触发器，其中两个串联连接，两个逻辑门一起形成同步电路，使得当输入命令信号以开始测试集成电路时，输出与标准时钟同步的分频时钟信号。

35. 发明授权

US4691331A Self-correcting frequency dividers 失效
标题翻译：自校正分频器
公开(公告)号：US4691331A
公开(公告)日：1987-09-01
申请号：US935170
申请日：1986-11-25
申请人： Robert J. Bayruns , Harry T. Weston
发明人： Robert J. Bayruns , Harry T. Weston
IPC分类号： H03K5/15 , H03K21/40 , H03K23/44 , H03K23/48 , H03K21/00 , H03K23/40
CPC分类号： H03K23/44 , H03K21/40 , H03K23/483 , H03K5/15093
摘要： A frequency divider for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate or NAND gate, respectively, connected for delivering its output to an n-bit delay device, the NOR or NAND gate further connected for receiving the output of the delay device as feedback at one of its two-input terminals and for receiving the n-bit counting stream at the other of its two-input terminals. The output of the delay device is then a 2n-bit counting stream.
摘要翻译：用于将n位周期性计数流（每个周期包含单个零或一个位，分别为n-1个或零个比特）转换成2n位计数流的分频器包括双输入NOR门或 NAND门分别连接用于将其输出传送到n位延迟器件，NOR或NAND门进一步连接用于接收延迟器件的输出作为其两输入端之一处的反馈，并用于接收n位在其两个输入端子的另一个处计数流。延迟器的输出就是一个2n位计数流。

36. 发明授权

US11468958B1 Shift register circuit and a method for controlling a shift register circuit 有权
公开(公告)号：US11468958B1
公开(公告)日：2022-10-11
申请号：US17344970
申请日：2021-06-11
申请人： Winbond Electronics Corp.
发明人： Kan-Yuan Cheng
IPC分类号： G11C19/00 , G11C19/28 , H03K23/42 , H03K23/40
摘要： A shift register circuit including a flip-flop chain and a control circuit is provided. The flip-flop chain is configured to receive an input signal and output an output signal. The control circuit is coupled to the flip-flop chain. The control circuit is configured to receive the input signal and the output signal and output a control signal to activate the flip-flop chain according to edge transitions of the input signal and the output signal. In addition, a method for controlling a shift register circuit is also provided.

37. 发明授权

US11329652B1 Loadable true-single-phase-clocking flop-based counter 有权
公开(公告)号：US11329652B1
公开(公告)日：2022-05-10
申请号：US17191704
申请日：2021-03-04
申请人： SHENZHEN GOODIX TECHNOLOGY CO., LTD.
发明人： Mohamed Elsayed , Scott D Willingham
IPC分类号： H03M1/56 , H03K23/40 , H04N5/3745
摘要： Techniques are described for implementing counter architectures to support high-speed, high-resolution pixel conversions, such as for CMOS image sensor applications. Embodiments implement a counter block that uses loadable true-signal-phase-clocking (L-TSPC) flops for at least a portion of the counter flops. Some embodiments support efficient two-phase pixel conversion by integrating counting, subtraction, and shifting out in the counter. For example, embodiments can perform a first high-speed pixel conversion phase to obtain a first conversion count. Prior to a second phase, the initial counter can be pre-subtracted by the amount of the first conversion count. Embodiments can then perform a second high-speed pixel conversion phase to obtain a second conversion count. As the second conversion count already has the first conversion count pre-subtracted, the second conversion count represents the final two-phase conversion result. Embodiments can read out this final two-phase conversion result as a digital output of the counter.

38. 发明申请

US20200382123A1 EVENT COUNTER CIRCUITS USING PARTITIONED MOVING AVERAGE DETERMINATIONS AND RELATED METHODS 审中-公开
公开(公告)号：US20200382123A1
公开(公告)日：2020-12-03
申请号：US16887560
申请日：2020-05-29
申请人： Syzexion Inc.
发明人： Gregory Michael Wright
IPC分类号： H03K23/40 , G06F11/30 , G06F11/34
摘要： An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system

39. 发明授权

US10326433B2 Clock filter and clock processing method 有权
公开(公告)号：US10326433B2
公开(公告)日：2019-06-18
申请号：US16135717
申请日：2018-09-19
申请人： Nuvoton Technology Corporation
发明人： Chun-Cheng Wang
IPC分类号： H03K5/1252 , H03K23/40 , H03K3/027 , G01R29/02
摘要： A clock filter filtering a glitch of an input clock to generate an output clock is provided. A first delay circuit inverts the input clock to generate an inverted clock and delays the inverted clock to generate a first processing clock. A second delay circuit delays the input clock to generate a second processing clock. A first setting circuit generates a reset clock according to the inverted clock and the first processing clock. A second setting circuit generates a set clock according to the input clock and the second processing clock. When the set clock changes from a first level to a second level, a third setting circuit sets the output clock at the second level. When the reset clock changes from the first level to the second level, the third setting circuit sets the output clock to the first level.

40. 发明申请

US20190155355A1 NETWORK SENSING DEVICE AND POWER MANAGEMENT METHOD THEREOF 审中-公开
公开(公告)号：US20190155355A1
公开(公告)日：2019-05-23
申请号：US15975824
申请日：2018-05-10
申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
发明人： SHUI-AN WEN , Shing-Wu Tung , Chun-Chih Chen , Shih-Tung Huang
IPC分类号： G06F1/32 , G06F1/30 , H03K23/40 , H04W52/02
摘要： A network sensing device is provided, which may include an active scheduling circuit and a sensor. The active scheduling circuit may operate regularly, and periodically generate a trigger signal. The sensor may include a power management circuit and a sensor circuit. The power management circuit may be coupled to the active scheduling circuit. The sensor circuit may be coupled to the power management circuit. The trigger signal may trigger the power management circuit, and the power management circuit may switch the sensor from a sleep mode to an active mode; the sensor circuit may collect the environmental information in the active mode, and the sensor may return to the sleep mode after the environmental information is saved.

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