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31. 发明授权

US4952527A Method of making buffer layers for III-V devices using solid phase epitaxy 失效
标题翻译：使用固相外延制备III-V器件缓冲层的方法
公开(公告)号：US4952527A
公开(公告)日：1990-08-28
申请号：US157806
申请日：1988-02-19
申请人： Arthur R. Calawa , Frank W. Smith , Michael J. Manfra , Chang-Lee Chen
发明人： Arthur R. Calawa , Frank W. Smith , Michael J. Manfra , Chang-Lee Chen
IPC分类号： H01L21/20 , H01L21/285 , H01L21/335 , H01L21/337 , H01L21/338 , H01L21/8252 , H01L29/10 , H01L29/51 , H01L29/812 , H01L31/09 , H01L31/18 , H01S5/02 , H01S5/026 , H01S5/223
CPC分类号： H01L29/517 , H01L21/02395 , H01L21/02463 , H01L21/02546 , H01L21/02631 , H01L21/02634 , H01L21/28587 , H01L21/8252 , H01L29/1075 , H01L29/66462 , H01L29/66863 , H01L29/66924 , H01L29/8128 , H01L31/09 , H01L31/184 , H01S5/0208 , H01S5/021 , H01S5/026 , H01S5/223 , Y02E10/544 , Y02P70/521 , Y10S148/003 , Y10S148/025 , Y10S148/041 , Y10S148/056 , Y10S148/154 , Y10S438/971
摘要： A new III-IV buffer material is described which is produced by low temperature growth of III-V compounds by MBE that has unique and desirable properties, particularly for closely spaced, submicron gate length active III-V semiconductor devices, such as HEMT's, MESFET's and MISFET's. In the case of the III-V material, GaAs, the buffer is grown under arsenic stable growth conditions, at a growth rate of 1 micron/hour, and at a substrate temperature preferably in the range of 150 to about 300.degree. C. The new material is crystalline, highly resistive, optically inactive, and can be overgrown with high quality III-V active layers.
摘要翻译：描述了新的III-IV缓冲材料，其通过MBE的III-V化合物的低温生长产生，其具有独特和期望的性质，特别是对于紧密间隔的亚微米栅极长度有源III-V半导体器件，例如HEMT，MESFET 和MISFET的。在III-V材料GaAs的情况下，缓冲液在砷稳定生长条件下以1微米/小时的生长速率和优选在150至约300℃的衬底温度下生长。新材料是结晶的，高度电阻的，光学上无活性的，并且可以用高质量的III-V有源层过度生长。

32. 发明授权

US4900372A III-V on Si heterostructure using a thermal strain layer 失效
标题翻译：使用热应变层的Si异质结构上的III-V
公开(公告)号：US4900372A
公开(公告)日：1990-02-13
申请号：US318169
申请日：1989-03-02
申请人： Jhang W. Lee , Richard E. McCullough
发明人： Jhang W. Lee , Richard E. McCullough
IPC分类号： H01L21/20 , H01L21/205
CPC分类号： H01L21/02573 , H01L21/0237 , H01L21/02455 , H01L21/02538 , H01L21/0262 , Y10S148/025 , Y10S148/097 , Y10S438/933 , Y10S438/938
摘要： A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.
摘要翻译：公开了一种在Si或Ge / Si衬底上生产具有III-V材料的沉积层的晶片的方法。该方法包括使用多个原位和非原位退火步骤以及形成热应变层以产生具有降低的缺陷发生率和平衡热应变的晶片。还公开了由此制造的晶片。

33. 发明授权

US4894349A Two step vapor-phase epitaxial growth process for control of autodoping 失效
标题翻译：用于控制自动掺杂的两步气相外延生长工艺
公开(公告)号：US4894349A
公开(公告)日：1990-01-16
申请号：US284512
申请日：1988-12-15
申请人： Yoshihiko Saito , Yoshiaki Matsushita
发明人： Yoshihiko Saito , Yoshiaki Matsushita
IPC分类号： H01L21/205 , H01L21/22 , H01L21/74
CPC分类号： H01L21/74 , H01L21/02381 , H01L21/0242 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/2205 , Y10S148/007 , Y10S148/025 , Y10S148/169
摘要： A process for forming a vapor-phase epitaxial growth layer on a silicon wafer having a buried layer of a high As or B concentration. This vapor-phase epitaxial growth process is performed in two steps of (i) performing a vapor-phase epitaxial growth at a relatively low temperature by using a reaction gas containing at least one kind selected from a group consisting of SiH.sub.x F.sub.4-x (x=0 to 3) and Si.sub.2 H.sub.x F.sub.6-x (x=0-5) and at least one kind selected from a group consisting of SiH.sub.4 and Si.sub.2 H.sub.6, and (ii) performing a vapor-phase epitaxial growth under a condition which allows a higher growth rate that in the step (i) by using a reaction gas containing SiH.sub.4 or Si.sub.2 H.sub.6 which may or may not be accompanied with silane fluoride.

34. 发明授权

US4870030A Remote plasma enhanced CVD method for growing an epitaxial semiconductor layer 失效
标题翻译：用于生长外延半导体层的远程等离子体增强CVD方法
公开(公告)号：US4870030A
公开(公告)日：1989-09-26
申请号：US100477
申请日：1987-09-24
申请人： Robert J. Markunas , Robert Hendry , Ronald A. Rudder
发明人： Robert J. Markunas , Robert Hendry , Ronald A. Rudder
IPC分类号： C23C16/22 , C23C16/452 , C30B25/10
CPC分类号： C30B25/105 , C23C16/22 , C23C16/452 , C30B29/06 , Y10S148/006 , Y10S148/025 , Y10S148/045
摘要： A remote plasma enhanced CVD apparatus and method for growing semiconductor layers on a substrate, wherein an intermediate feed gas, which does not itself contain constituent elements to be deposited, is first activated in an activation region to produce plural reactive species of the feed gas. These reactive species are then spatially filtered to remove selected of the reactive species, leaving only other, typically metastable, species which are then mixed with a carrier gas including constituent elements to be deposited on the substrate. During this mixing, the selected spatially filtered reactive species of the feed gas chemically interacts, i.e., partially dissociates and activates, in the gas phase, the carrier gas, with the process variables being selected so that there is no back-diffusion of gases or reactive species into the feed gas activation region. The dissociated and activated carrier gas along with the surviving reactive species of the feed gas then flows to the substrate. At the substrate, the surviving reactive species of the feed gas further dissociate the carrier gas and order the activated carrier gas species on the substrate whereby the desired epitaxial semiconductor layer is grown on the substrate.
摘要翻译：用于在衬底上生长半导体层的远程等离子体增强CVD装置和方法，其中首先在活化区域中激活不本身含有待沉积的构成元素的中间进料气体，以产生多种进料气体的反应性物质。然后将这些反应性物质进行空间过滤以除去所选择的反应性物质，仅留下其它通常为亚稳态的物质，然后将其与包含待沉积在基底上的构成元素的载气混合。在该混合期间，所选择的空间过滤的进料气体的反应性物质在气相中化学相互作用，即在气相中部分解离并活化载气，其中选择工艺变量，使得不存在气体的反向扩散或反应性物质进入进料气体活化区域。然后将解离和活化的载气与进料气体的存活反应性物质一起流入基材。在衬底上，进料气体的存活的反应性物质进一步离解载气并且将活化的载气物质排列在衬底上，从而在衬底上生长期望的外延半导体层。

35. 发明授权

US4859626A Method of forming thin epitaxial layers using multistep growth for autodoping control 失效
标题翻译：使用多步增长形成自动掺杂控制的薄外延层的方法
公开(公告)号：US4859626A
公开(公告)日：1989-08-22
申请号：US202731
申请日：1988-06-03
申请人： Rick L. Wise
发明人： Rick L. Wise
IPC分类号： H01L21/20 , H01L21/22
CPC分类号： H01L21/2205 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/0262 , Y10S148/007 , Y10S148/015 , Y10S148/025 , Y10S148/029
摘要： A method of forming thin epitaxial layers by subjecting a substrate to a high temperature prebake followed by a medium temperature capping seal and a low temperature deposition is disclosed. In a preferred embodiment the epitaxial layer is formed by low pressure chemical vapor deposition of dichlorosilane. The method has been demonstrated to alleviate the increase in autodoping and epitaxial defects normally associated with lowering the deposition temperature.
摘要翻译：公开了一种通过对衬底进行高温预烘烤，然后进行中温封盖密封和低温沉积来形成薄外延层的方法。在优选的实施方案中，通过二氯硅烷的低压化学气相沉积形成外延层。已经证明该方法可以减轻通常与沉积温度降低相关的自掺杂和外延缺陷的增加。

36. 发明授权

US4588451A Metal organic chemical vapor deposition of 111-v compounds on silicon 失效
标题翻译： 111-v化合物在硅上的金属有机化学气相沉积
公开(公告)号：US4588451A
公开(公告)日：1986-05-13
申请号：US604835
申请日：1984-04-27
申请人： Stanley M. Vernon
发明人： Stanley M. Vernon
IPC分类号： H01L21/205 , H01L27/14 , H01L29/267 , H01L31/0304 , H01L31/18
CPC分类号： H01L31/18 , H01L21/02381 , H01L21/02546 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02658 , H01L29/267 , H01L31/03042 , H01L31/03046 , Y02E10/544 , Y10S148/025 , Y10S148/059 , Y10S148/072 , Y10S148/11 , Y10S438/933
摘要： Expitaxial composite comprising thin films of a Group III-V compound semiconductor such as gallium arsenide (GaAs) or gallium aluminum arsenide (GaAlAs) on single crystal silicon substrates are disclosed. Also disclosed is a process for manufacturing, by chemical deposition from the vapor phase, epitaxial composites as above described, and to semiconductor devices based on such epitaxial composites. The composites have particular utility for use in making light sensitive solid state solar cells.
摘要翻译：公开了包含III-V族化合物半导体如砷化镓（GaAs）或砷化镓砷（GaAlAs）在单晶硅衬底上的薄膜的外延复合材料。还公开了通过从气相的化学沉积，如上所述的外延复合材料以及基于这种外延复合材料的半导体器件制造方法。该复合材料具有用于制造光敏固态太阳能电池的特殊用途。

37. 发明授权

US4528047A Method for forming a void free isolation structure utilizing etch and refill techniques 失效
标题翻译：使用蚀刻和再填充技术形成无空隙隔离结构的方法
公开(公告)号：US4528047A
公开(公告)日：1985-07-09
申请号：US624425
申请日：1984-06-25
申请人： Klaus D. Beyer , Victor J. Silvestri
发明人： Klaus D. Beyer , Victor J. Silvestri
IPC分类号： H01L21/76 , H01L21/20 , H01L21/74 , H01L21/763 , H01L21/302
CPC分类号： H01L21/743 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/763 , Y10S148/025 , Y10S148/026 , Y10S148/05 , Y10S148/085
摘要： A void-free isolated semiconductor substrate is described which contains a pattern of substantially vertically sided trenches within a semiconductor body. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to a level from the upper surface of the trenches as specified approximately by the equation:y=0.34xwhere y is the distance between the epitaxial layer and the top surface and x is the trench width. The preferred range for the trench width x is about 10 micrometers or less. A polycrystalline silicon layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer. A second insulating layer is located on the polycrystalline silicon layer within the trenches for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The polycrystalline silicon layer above the epitaxial layer completely covers the undesirable sharp faceted structure at the top of the epitaxial semiconductor growth structure.
摘要翻译：描述了一种无空隙的隔离半导体衬底，其包含半导体本体内的基本上垂直的沟槽的图案。隔离沟槽的图案隔离可能包含有源和无源半导体器件的单晶半导体材料的区域。第一绝缘层位于沟槽的侧壁上。沟槽的底部或底部对单晶半导体体是开放的。从沟槽的底部延伸的外延层将沟槽的图案从沟槽的上表面填充到高达一定水平，如以下等式所规定的：y = 0.34x其中y是外延层和顶表面之间的距离 x是沟槽宽度。沟槽宽度x的优选范围为约10微米或更小。多晶硅层填充在外延层的上表面上方的沟槽图案的附加部分。第二绝缘层位于沟槽内的多晶硅层上，用于隔离沟槽图案与环境。密封的外延单晶半导体防止在沟槽图案内形成空隙。外延层上方的多晶硅层完全覆盖外延半导体生长结构顶部的不期望的尖锐刻面结构。

38. 发明授权

US4233092A Utilizing lead compounds of sulphur, selenium and tellurium as dopant sources 失效
标题翻译：利用硫，硒和碲的铅化合物作为掺杂源
公开(公告)号：US4233092A
公开(公告)日：1980-11-11
申请号：US74617
申请日：1979-09-12
申请人： Jeffrey J. Harris , Colin E. C. Wood
发明人： Jeffrey J. Harris , Colin E. C. Wood
IPC分类号： C30B23/08 , C30B23/02 , C30B29/42 , H01L21/203 , H01L29/207
CPC分类号： H01L21/02631 , C30B23/02 , H01L21/02546 , H01L21/02576 , Y10S148/025 , Y10S148/169 , Y10S252/951
摘要： A method of growing an n-type GaAs layer on a substrate by a molecular beam epitaxy process, the dopant consisting of S, Se or Te. The layer is prepared by directing molecular beams of gallium, arsenic and PbX, where X is S, Se or Te, onto a heated substrate. It has not proved practicable to grow an n-type GaAs layer by molecular beam epitaxy using S, Se or Te as dopant in the form of a molecular beam consisting of elemental S, Se or Te.
摘要翻译：通过分子束外延法在衬底上生长n型GaAs层的方法，由S，Se或Te组成的掺杂剂。该层通过将镓，砷和PbX的分子束（其中X是S，Se或Te）引导到加热的衬底上来制备。通过分子束外延生长n型GaAs层，使用S，Se或Te作为由元素S，Se或Te组成的分子束形式的掺杂剂，尚未证明是切实可行的。

39. 发明授权

US4143178A Manufacturing method of semiconductor devices 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US4143178A
公开(公告)日：1979-03-06
申请号：US813464
申请日：1977-07-07
申请人： Nozomu Harada , Nobuhisa Kubota
发明人： Nozomu Harada , Nobuhisa Kubota
IPC分类号： H01L27/088 , H01L21/28 , H01L21/3215 , H01L21/339 , H01L21/768 , H01L21/8234 , H01L27/108 , H01L27/115 , H01L29/417 , H01L29/78 , H01L21/225 , B05D5/12
CPC分类号： H01L29/66954 , H01L21/32155 , H01L21/768 , H01L27/10805 , H01L27/115 , Y10S148/025 , Y10S148/051 , Y10S148/053 , Y10S148/117 , Y10S148/122
摘要： A manufacturing method of semiconductor device having a single layer or multilayer of polycrystalline semiconductor including doped impurity is provided which comprises a step of forming a first polycrystalline semiconductor layer with doped impurity on a semiconductor substrate and another step of forming a second polycrystalline semiconductor layer without doped impurity on the first polycrystalline semiconductor layer. The manufacturing method of the invention provides excellent MOS FET's in the semiconductor device of which the threshold voltage varies little. High reliable semiconductor device may further be manufactured with a high yield.

40. 发明授权

US4091138A Insulating film, sheet, or plate material with metallic coating and method for manufacturing same 失效
标题翻译：绝缘膜，片材或板材与金属涂层及其制造方法
公开(公告)号：US4091138A
公开(公告)日：1978-05-23
申请号：US655233
申请日：1976-02-04
申请人： Toshinori Takagi , Tatsuichiro Nishiyama , Unosuke Uchida
发明人： Toshinori Takagi , Tatsuichiro Nishiyama , Unosuke Uchida
IPC分类号： C23C14/02 , C23C14/32 , H01B13/00 , H05K3/14 , C23C13/02
CPC分类号： H05K3/146 , C23C14/02 , C23C14/32 , H01B13/0026 , Y10S148/025 , Y10S148/045 , Y10S148/169 , Y10S174/33 , Y10T428/24917 , Y10T428/31681
摘要： This invention provides a method for forming a dense, electrically conductive, metallic coating having a sufficient adherence without use of an adhesive on an insulating film, sheet, or plate such as plastic film, plastic rigid sheet, or ceramics by the cluster ion plating procedure which comprises heating a crucible containing a vapor deposition metal at a temperature of 200.degree. to 2,500.degree. C in a vacuum of 1 .times. 10.sup.-4 Torr. to 1 .times. 10.sup.-7 Torr. to generate a metal cluster through a small hole of the crucible, ionizing the metal cluster by the impact of electrons, and electrostatically accelerating the resulting cluster ion and depositing the same on a base material; a method for directly forming an electric circuit on the base material without use of adhesive according to the above-said method, wherein the base material is covered with a mask in the sheet form; and a method for efficiently increasing the thickness of the metallic coatings formed by the above methods, by further deposition of a metal by a vacuum deposition procedure or by an ion plating procedure similar to the said cluster ion plating, except that the crucible has an ejecting hole of a larger diameter so that practically the cluster is no more formed. The invention also provides the products manufactured by the above methods.
摘要翻译：本发明提供一种用于形成致密的，导电的金属涂层的方法，其具有足够的粘附性，而不使用绝缘膜，片或板上的粘合剂，例如塑料膜，塑料刚性片或陶瓷，通过簇离子电镀程序其包括在1×10 -4 Torr的真空中在200℃至2500℃的温度下加热含有气相沉积金属的坩埚。至1×10-7乇。通过坩埚的小孔产生金属簇，通过电子的撞击使金属簇电离，并静电加速得到的簇离子并将其沉积在基材上; 根据上述方法，在不使用粘合剂的情况下在基材上直接形成电路的方法，其中基材被片状的掩模覆盖; 以及通过上述方法形成的金属涂层的厚度的方法，通过真空沉积程序进一步沉积金属或通过类似于所述簇离子镀的离子镀工艺，除了坩埚具有喷射较大直径的孔，使得实际上不再形成簇。本发明还提供通过上述方法制造的产品。

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