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31. 发明授权

US09979395B2 Precision modulation timer (PMT) integrated in a programmable logic device 有权
公开(公告)号：US09979395B2
公开(公告)日：2018-05-22
申请号：US15656978
申请日：2017-07-21
申请人： AnDAPT, Inc.
发明人： Patrick J. Crotty , Kapil Shankar , John Birkner
IPC分类号： H03K19/173 , H03K19/177 , H03K19/0175 , H03K5/131 , H03K5/135 , H03K5/00 , H03K19/00
CPC分类号： H03K19/017581 , H03K5/131 , H03K5/135 , H03K19/0016 , H03K19/017509 , H03K2005/00078 , H03K2005/00247
摘要： A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.

32. 发明授权

US09979384B2 Timing adjustment method for drive circuit and timing adjustment circuit for drive circuit 有权
公开(公告)号：US09979384B2
公开(公告)日：2018-05-22
申请号：US15122438
申请日：2015-04-02
申请人： DENSO CORPORATION
发明人： Atsushi Kobayashi , Kiyoshi Yamamoto , Atsushi Kanamori , Sadahiro Akama
IPC分类号： H03K19/00 , H03K17/16 , H03K3/012 , H03K5/1534 , H03K17/28
CPC分类号： H03K17/162 , G11C29/023 , G11C29/028 , H03K3/012 , H03K5/1534 , H03K17/163 , H03K17/168 , H03K17/28 , H03K2005/00065 , H03K2005/00247 , H03K2005/00273
摘要： A timing adjustment method for a drive circuit, including: a rise detector for a rise start when a voltage-driven semiconductor element is turned off; a timing signal output unit outputting a speed change timing signal after a set delay time has elapsed from the rise start; and a conduction controller for a conduction control terminal of the semiconductor element using the timing signal, comprises: defining an estimated terminal voltage of the conduction control terminal when a rise completion time elapses; increasing a delay time by a predetermined unit time, and changing the drive signal to a turning off level again, when the conduction control terminal doesn't fall below the estimated terminal voltage after the drive signal is changed to a turning off level before the level is inverted; and determining a delay time, when the conduction control terminal falls below the estimated terminal voltage initially, as a set value.

33. 发明申请

US20180026637A1 PRECISION MODULATION TIMER (PMT) INTEGRATED IN A PROGRAMMALBE LOGIC DEVICE 有权
公开(公告)号：US20180026637A1
公开(公告)日：2018-01-25
申请号：US15656978
申请日：2017-07-21
申请人： AnDAPT, Inc.
发明人： Patrick J. CROTTY , Kapil SHANKAR , John BIRKNER
IPC分类号： H03K19/0175 , H03K5/135 , H03K5/131
CPC分类号： H03K19/017581 , H03K5/131 , H03K5/135 , H03K19/0016 , H03K19/017509 , H03K2005/00078 , H03K2005/00247
摘要： A timer block includes: a digital control block including a mode selector and a register loading a time delay; a counter coupled to the register of the digital control block, wherein the counter loads a counter value corresponding to the time delay based on an operational mode selected by the mode selector and generates a digital output indicating the counter value that is decremented at each clock; and a pulse generator configured to generate a pulse signal based on the counter value of the counter. The timer block is integrated in a programmable logic device (PLD) including a programmable fabric and a signal wrapper that is configured to provide signals between the timer block and the programmable fabric. The operational mode of the timer block is programmably configured using the programmable fabric and the signal wrapper.

34. 发明申请

US20170322730A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 审中-公开
公开(公告)号：US20170322730A1
公开(公告)日：2017-11-09
申请号：US15655336
申请日：2017-07-20
申请人： Conversant Intellectual Property Management Inc.
发明人： Peter B. GILLINGHAM , Graham ALLAN
IPC分类号： G06F3/06 , G11C16/32 , G11C16/28 , G11C16/10 , G11C7/22 , G11C7/10 , G06F13/16 , G11C14/00 , G11C16/04 , H03K5/00
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

35. 发明授权

US09520864B2 Delay structure for a memory interface 有权
标题翻译：存储器接口的延迟结构
公开(公告)号：US09520864B2
公开(公告)日：2016-12-13
申请号：US14298742
申请日：2014-06-06
申请人： QUALCOMM Incorporated
发明人： Jan Christian Diffenderfer , Yuehchun Claire Cheng
IPC分类号： H03K5/13 , G11C7/10 , H03K5/135 , H03K5/00
CPC分类号： H03K5/13 , G11C7/1072 , H03K5/131 , H03K5/135 , H03K2005/00026 , H03K2005/00247 , H03K2005/00286
摘要： Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.
摘要翻译：本文描述了用于延迟信号的系统和方法。在一个实施例中，一种用于延迟信号的方法包括接收第一信号边缘，并且响应于接收到第一信号边沿，对振荡器的振荡次数进行计数。该方法还包括如果振荡次数达到预定数量则输出第二信号沿。第二信号边缘表示第一信号边沿的延迟版本。

36. 发明授权

US09124256B2 Tunable clock system 有权
标题翻译：可调时钟系统
公开(公告)号：US09124256B2
公开(公告)日：2015-09-01
申请号：US14589444
申请日：2015-01-05
申请人： Laurence H. Cooke
发明人： Laurence H. Cooke
IPC分类号： H03K3/00 , H03K5/13 , H03K5/00
CPC分类号： H03K5/15 , H03K5/131 , H03K5/133 , H03K5/15013 , H03K2005/00065 , H03K2005/00247
摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
摘要翻译：由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中可能是因为例如深亚微米器件和互连中的物理变化。还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

37. 发明申请

US20150109039A1 TUNABLE CLOCK SYSTEM 审中-公开
标题翻译：时钟系统
公开(公告)号：US20150109039A1
公开(公告)日：2015-04-23
申请号：US14589444
申请日：2015-01-05
申请人： Laurence H. COOKE
发明人： Laurence H. COOKE
IPC分类号： H03K5/13
CPC分类号： H03K5/15 , H03K5/131 , H03K5/133 , H03K5/15013 , H03K2005/00065 , H03K2005/00247
摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.
摘要翻译：由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中可能是因为例如深亚微米器件和互连中的物理变化。还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

38. 发明申请

US20100097114A1 PULSE WIDTH MODULATION CIRCUIT AND LIQUID JET PRINTING APPARATUS 有权
标题翻译：脉冲宽度调制电路和液体喷射印刷设备
公开(公告)号：US20100097114A1
公开(公告)日：2010-04-22
申请号：US12582766
申请日：2009-10-21
申请人： Shinichi MIYAZAKI , Hiroyuki YOSHINO , Nobuaki AZAMI , Atsushi OSHIMA , Noritaka IDE , Kunio TABATA
发明人： Shinichi MIYAZAKI , Hiroyuki YOSHINO , Nobuaki AZAMI , Atsushi OSHIMA , Noritaka IDE , Kunio TABATA
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , B41J2/04541 , B41J2/04581 , B41J2/04588 , B41J2/04593 , B41J2/04596 , H03K5/15013 , H03K2005/00247
摘要： A pulse width modulation circuit includes: a reference signal generator which generates a plurality of mutually differing reference signals; a comparator which compares the reference signals and an input signal with respect to magnitude, and outputs results of the comparison as a plurality of comparison signals with mutually differing phases; and a synthesizer which, using a logical operation, outputs the plurality of comparison signals output from the comparator as a pulse width modulated signal configured of one or more binary signals.
摘要翻译：脉冲宽度调制电路包括：参考信号发生器，其生成多个相互不同的参考信号; 比较器，比较参考信号和输入信号相对于幅度，并将比较结果作为具有相互不同相位的多个比较信号; 以及合成器，其使用逻辑运算将从比较器输出的多个比较信号作为由一个或多个二进制信号配置的脉宽调制信号输出。

39. 发明申请

US20090167378A1 Method and System for Providing a Power-On Reset Pulse 有权
标题翻译：提供上电复位脉冲的方法和系统
公开(公告)号：US20090167378A1
公开(公告)日：2009-07-02
申请号：US12400567
申请日：2009-03-09
申请人： Alireza Zolfaghari
发明人： Alireza Zolfaghari
IPC分类号： H03L7/00
CPC分类号： H03K17/22 , H03K2005/00247
摘要： Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.
摘要翻译：提供一种用于提供上电复位脉冲的方法和系统。该系统包括电平检测器，其被配置为当输入信号达到预定电平时接收输入信号并产生至少间接的复位信号。该系统还包括具有计数特性并被配置为接收复位信号和时钟信号的计数器。计数器根据计数特性，时钟信号和接收到的复位信号产生延迟信号。

40. 发明授权

US07477112B1 Structure for the main oscillator of a counter-controlled delay line 有权
标题翻译：反控制延时线主振荡器的结构
公开(公告)号：US07477112B1
公开(公告)日：2009-01-13
申请号：US11505696
申请日：2006-08-16
申请人： Tao Pi , Alireza S. Kaviani , Robert M. Ondris
发明人： Tao Pi , Alireza S. Kaviani , Robert M. Ondris
IPC分类号： H03B27/00
CPC分类号： H03K5/131 , H03K3/0315 , H03K2005/00058 , H03K2005/00247 , H03L7/0814
摘要： A counter-controlled delay line includes a main oscillator for delaying edges of an input signal to generate a main clock signal. The main oscillator includes a plurality of gated delay elements connected in a ring. Each gated delay element includes a first control terminal to receive a corresponding load signal, and includes a second control terminal to receive a release signal. The release signal may simultaneously enable and disable state transitions in all delay elements, and the load signals may simultaneously drive an output of each delay element to any selected logic state.
摘要翻译：反向控制的延迟线包括用于延迟输入信号的边沿以产生主时钟信号的主振荡器。主振荡器包括以环形连接的多个门控延迟元件。每个门控延迟元件包括用于接收相应的负载信号的第一控制端子，并且包括用于接收释放信号的第二控制端子。释放信号可以同时启用和禁用所有延迟元件中的状态转换，并且负载信号可以同时将每个延迟元件的输出驱动到任何选择的逻辑状态。

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