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31. 发明授权

US08886696B1 Digital signal processing circuitry with redundancy and ability to support larger multipliers 有权
标题翻译：数字信号处理电路具有冗余和支持较大乘法器的能力
公开(公告)号：US08886696B1
公开(公告)日：2014-11-11
申请号：US12380853
申请日：2009-03-03
申请人： Martin Langhammer
发明人： Martin Langhammer
IPC分类号： G06F7/52 , H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： G06F7/52 , G06F7/5324 , G06F7/5443 , G06F11/08 , G06F2207/382 , H01L25/00 , H01L2924/0002 , H03K19/173 , H03K19/177 , H01L2924/00
摘要： Digital signal processing (“DSP”) circuit blocks that include multipliers of a certain basic size are augmented to enable the DSP block to perform multiplications that are larger than the basic multiplier size would otherwise permit. In some embodiments, the larger multiplication can have less than full precision. In other embodiments, the larger multiplication can have full precision by making use of some capabilities of a second DSP block.
摘要翻译：包括特定基本尺寸的乘法器的数字信号处理（“DSP”）电路块被增加以使得DSP块执行大于基本乘法器大小否则将允许的乘法。在一些实施例中，较大的乘法可具有小于全精度。在其他实施例中，通过利用第二DSP块的某些能力，较大乘法可以具有完全的精度。

32. 发明授权

US08854079B2 Error detection in nonvolatile logic arrays using parity 有权
标题翻译：使用奇偶校验的非易失性逻辑阵列中的错误检测
公开(公告)号：US08854079B2
公开(公告)日：2014-10-07
申请号：US13753856
申请日：2013-01-30
申请人： Texas Instruments Incorporated
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： H03K19/177 , G06F7/00 , H03K19/173
CPC分类号： H03K19/173
摘要： A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.
摘要翻译：片上系统（SoC）具有耦合到一个或多个核心逻辑块的n行m列的非易失性存储器阵列。 M被限制为奇数。每次写入一行m个数据位时，使用m个数据位来计算奇偶校验。在存储奇偶校验位之前，它被反转。每次读取一行时，检查奇偶校验以确定恢复的数据位中是否存在奇偶校验错误。当检测到奇偶校验错误时，在SoC上执行引导操作。

33. 发明授权

US08803552B2 Reconfigurable sequencer structure 有权
标题翻译：可重新配置的音序器结构
公开(公告)号：US08803552B2
公开(公告)日：2014-08-12
申请号：US13626047
申请日：2012-09-25
申请人： Pact XPP Technologies AG
发明人： Martin Vorbach
IPC分类号： H03K19/173 , G06F15/78
CPC分类号： G06F15/7867 , G06F9/30145 , G06F13/16 , G06F13/36 , G06F13/4068 , H03K19/173
摘要： A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.
摘要翻译：描述用于数据处理的单元元素字段，具有用于执行代数和/或逻辑功能的功能单元装置和用于接收，存储和/或输出信息的存储单元装置。形成功能单元 - 存储单元组合，其中控制连接从功能单元装置引导到存储单元装置。

34. 发明授权

US08766665B2 Reconfigurable logic automata 有权
标题翻译：可重构逻辑自动机
公开(公告)号：US08766665B2
公开(公告)日：2014-07-01
申请号：US13226484
申请日：2011-09-06
申请人： David Allen Dalrymple , Erik Demaine , Neil Gershenfeld , Forrest Green , Ara Knaian
发明人： David Allen Dalrymple , Erik Demaine , Neil Gershenfeld , Forrest Green , Ara Knaian
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/173 , G06F7/388 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17748
摘要： A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A reconfigurable asynchronous logic cell comprises a set of one-bit buffers for communication with at least one neighboring cell, each buffer capable of having several states and configured for receiving input state tokens from neighboring cells and for transferring output state tokens to neighboring cells, and a one-bit processor configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, wherein the logic operation and the functional configuration of the buffers are reconfigurably programmable. A reconfigurable logic circuit comprises a plurality of reconfigurable logic cells that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic cells.
摘要翻译：与其最近的邻居交互的可重新配置的异步逻辑元件系列允许在位级异步的电路的可重构实现。可重新配置的异步逻辑单元包括一组用于与至少一个相邻单元进行通信的缓冲器，每个缓冲器能够具有多个状态并被配置用于从相邻小区接收输入状态令牌并将输出状态令牌传送到相邻小区，以及配置为执行利用接收的令牌作为输入的逻辑操作并产生反映逻辑操作的结果的输出令牌的一位处理器，其中缓冲器的逻辑操作和功能配置可重新配置地可编程。可重配置逻辑电路包括多个可重构逻辑单元，其通过本地通过状态令牌来计算，并且通过相邻逻辑单元的编程指令的定向移位来重新配置。

35. 发明授权

US08760931B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08760931B2
公开(公告)日：2014-06-24
申请号：US14033924
申请日：2013-09-23
申请人： Semiconductor Engery Laboratory Co., Ltd.
发明人： Yasuhiko Takemura , Shunpei Yamazaki
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： H03K19/0013 , H01L27/0629 , H01L29/7869 , H01L2924/0002 , H03K17/161 , H03K19/173 , H03K19/17724 , H03K19/17736 , H03K19/1776 , H03K19/17772 , H03K19/17784 , H01L2924/00
摘要： It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.
摘要翻译：本发明的目的是提供能够降低功耗的半导体装置。另一个目的是提供使用诸如可编程逻辑器件（PLD）之类的编程单元的高度可靠的半导体器件。根据基本块之间的连接配置的变化，改变基本块的供电电压。也就是说，当基本块之间的连接结构使得基本块不对电路有贡献时，停止向该基本块提供电源电压。此外，使用使用使用氧化物半导体形成沟道形成区域的场效应晶体管形成的编程单元来控制对基本块的电源电压的供给，场效应晶体管具有极低的截止电流或极低漏电流。

36. 发明授权

US08736303B2 PSOC architecture 有权
标题翻译： PSOC架构
公开(公告)号：US08736303B2
公开(公告)日：2014-05-27
申请号：US13328385
申请日：2011-12-16
申请人： Warren Snyder , Monte Mar
发明人： Warren Snyder , Monte Mar
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/08 , G06F1/08 , G06F1/32 , G06F15/7867 , G06G7/06 , H03B5/364 , H03K3/012 , H03K3/014 , H03K3/02315 , H03K19/173 , H03K19/1733 , H03K19/177 , H03K19/17736 , H03K19/17748
摘要： A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.
摘要翻译：具有多个模拟电路块的电路，每个模拟电路块被配置为提供至少一个模拟功能，以及耦合模拟电路块的可编程互连，并且可配置为将模拟电路块的组合彼此互连。电路形成在集成电路（芯片）中，并且可编程互连包括耦合在模拟电路块和提供芯片的信号连接的端口之间的多个开关。

37. 发明授权

US08681573B2 Programmable/re-programmable device in high-k metal gate MOS 有权
标题翻译：高k金属门MOS中的可编程/可重新编程器件
公开(公告)号：US08681573B2
公开(公告)日：2014-03-25
申请号：US13870598
申请日：2013-04-25
申请人： Intel Corporation
发明人： Walid M. Hafez , Anisur Rahman , Chia-Hong Jan
IPC分类号： G11C7/22
CPC分类号： G11C7/00 , G11C17/16 , G11C17/18 , H03K19/173
摘要： Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.
摘要翻译：公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

38. 发明申请

US20140028347A1 IMPLEMENTING LOGIC CIRCUITS WITH MEMRISTORS 有权
标题翻译：用电磁阀实现逻辑电路
公开(公告)号：US20140028347A1
公开(公告)日：2014-01-30
申请号：US13561978
申请日：2012-07-30
申请人： Warren Robinett , R. Stanley Williams
发明人： Warren Robinett , R. Stanley Williams
IPC分类号： H03K19/173
CPC分类号： H03K19/173 , G11C13/0007 , H03K19/17712 , H03K19/17728
摘要： Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.
摘要翻译：使用忆阻器实现逻辑可以包括在逻辑单元中具有至少三个忆阻器和偏置电阻器的电路。至少三个忆阻器中的一个是逻辑单元内的输出忆阻器，至少三个忆阻器的其他忆阻器是输入忆阻器。至少三个忆阻器和偏置电阻器中的每一个电连接到电压源，其中施加到至少三个忆阻器中的每一个的每个电压和至少三个忆阻器的偏置电阻器和电阻状态确定输出忆阻器的电阻状态。

39. 发明授权

US08601424B1 Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 有权
公开(公告)号：US08601424B1
公开(公告)日：2013-12-03
申请号：US12893904
申请日：2010-09-29
申请人： Michael D. Hutton , Gregg William Baeckler , Jinyong Yuan , Chris Wysocki , Pouyan Djahani
发明人： Michael D. Hutton , Gregg William Baeckler , Jinyong Yuan , Chris Wysocki , Pouyan Djahani
IPC分类号： G06F17/50
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

40. 发明申请

US20130278289A1 Method and Apparatus for Improving Efficiency of Programmable Logic Circuit Using Cascade Configuration 审中-公开
标题翻译：使用级联配置提高可编程逻辑电路效率的方法和装置
公开(公告)号：US20130278289A1
公开(公告)日：2013-10-24
申请号：US13865851
申请日：2013-04-18
申请人： Te-Tse Jang , James F. Rogers
发明人： Te-Tse Jang , James F. Rogers
IPC分类号： H03K19/173
CPC分类号： H03K19/173 , H03K19/17728
摘要： An integrated circuit (“IC”) device capable of programmably performing user selected functions is disclosed. The IC device, in one embodiment, includes multiple input output (“I/O”) blocks, programmable interconnection blocks (“PIBs”), and programmable logic blocks (“PLBs”). While the I/O blocks can be selectively coupled to one of I/O pads, the PIB blocks can be selectively coupled to at least a portion of the I/O blocks. Each of the PLBs, in one aspect, is configured to have at least two programmable look-up tables (“LUTs”). The programmable LUTs are connected in a cascade configuration via a dedicated programmable wire (“DPW”).
摘要翻译：公开了一种能够可编程地执行用户选择的功能的集成电路（“IC”）装置。在一个实施例中，IC器件包括多个输入输出（“I / O”）块，可编程互连块（“PIB”）和可编程逻辑块（“PLB”）。虽然I / O块可以选择性地耦合到I / O焊盘中的一个，但是PIB块可以选择性地耦合到I / O块的至少一部分。在一个方面，每个PLB被配置为具有至少两个可编程查询表（“LUT”）。可编程LUT通过专用可编程线（“DPW”）以级联配置连接。

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