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    • 32. 发明授权
    • ESD protection structure
    • ESD保护结构
    • US08981482B2
    • 2015-03-17
    • US13241079
    • 2011-09-22
    • Xiang Gao
    • Xiang Gao
    • H01L29/772H01L27/02H01L29/08H01L29/10H01L29/74H01L29/06H01L29/749H01L29/78
    • H01L27/027H01L29/0649H01L29/0834H01L29/1016H01L29/7436H01L29/749H01L29/7835
    • A device used as an ESD protection structure, which is a modified N-type LDMOS device is disclosed. A conventional LDMOS includes only one N-type heavily doped region as a drain in an N-type lightly doped region (11), while the device of the invention includes a P-type heavily doped region (22) in an N-type lightly doped region (11), dividing the N-type heavily doped region into two N-type heavily doped regions (21, 23) unconnected and independent to each other. The N-type heavily doped region (21) close to the gate (14) has no picking-up terminal. The N-type heavily doped region (23) away from the gate (14) together with the P-type heavily doped region (22) is picked up and connected to an input/output bonding pad.
    • 公开了一种用作ESD保护结构的器件,其是修改的N型LDMOS器件。 常规LDMOS在N型轻掺杂区域(11)中仅包括一个N型重掺杂区域作为漏极,而本发明的器件包括N型轻掺杂区域中的P型重掺杂区域(22) 掺杂区域(11),将N型重掺杂区域划分成彼此不连接和独立的两个N型重掺杂区域(21,23)。 接近栅极(14)的N型重掺杂区域(21)没有拾取端子。 与P型重掺杂区域(22)一起离开栅极(14)的N型重掺杂区域(23)被拾取并连接到输入/输出接合焊盘。
    • 37. 发明授权
    • Semiconductor device
    • 半导体器件
    • US06472692B1
    • 2002-10-29
    • US09566737
    • 2000-05-09
    • Katsumi SatohKazuhiro MorishitaShinji Koga
    • Katsumi SatohKazuhiro MorishitaShinji Koga
    • H01L2974
    • H01L29/744H01L29/1016
    • To suppress spike voltage generated at turn-off operation, a semiconductor device according to the invention comprises a first region composed of a first conductor, a second region composed of a second conductor formed on top of the first region, a third region composed of the first conductor formed on top of the second region and a fourth region composed of the second conductor formed on top of the third region. The second region is comprised of a depletion-layer forming auxiliary layer having a short lifetime and formed in the vicinity of the third region, a tail-current suppression layer having a shorter lifetime than that of the depletion-layer forming auxiliary layer and formed in the vicinity of the first region and a depletion-layer forming suppression layer having a longer lifetime than that of the depletion-layer forming auxiliary layer and formed between the depletion-layer forming auxiliary layer and the tail-current suppression layer.
    • 为了抑制在关断操作时产生的尖峰电压,根据本发明的半导体器件包括由第一导体构成的第一区域,由形成在第一区域的顶部上的第二导体构成的第二区域,由 第一导体形成在第二区域的顶部上,第四区域由形成在第三区域的顶部上的第二导体构成。 第二区域由具有短寿命且在第三区域附近形成的耗尽层形成辅助层构成,具有比耗尽层形成辅助层的寿命短的尾电流抑制层,并形成在 形成在耗尽层形成辅助层和尾流抑制层之间的第一区域附近和耗尽层形成抑制层的寿命比耗尽层形成辅助层的寿命更长。
    • 40. 发明授权
    • Semiconductor devices employing conductivity modulation
    • 采用电导率调制的半导体器件
    • US4831423A
    • 1989-05-16
    • US119304
    • 1987-11-06
    • John M. Shannon
    • John M. Shannon
    • H01L29/78H01L21/331H01L27/12H01L29/06H01L29/08H01L29/10H01L29/73H01L29/732H01L29/739
    • H01L29/0619H01L29/0684H01L29/0821H01L29/1016H01L29/7393
    • A semiconductor device, e.g. a lateral DMOS transistor or bipolar transistor, has a main current path (20) extending through a high resistivity body portion (1) of one conductivity type. A minority-carrier injector region (6) which may be of the opposite conductivity type is provided in the body portion (1) in the vicinity of the current path (20) and serves with an applied forward-bias to inject minority charge carriers (16) which are characteristic of the opposite conductivity type into the body portion (1) to modulate the conductivity of the current path (20). In accordance with the invention one or more further regions (8) of the opposite conductivity type are located in the part of the body portion (1) in the vicinity of the current path (20) and within a minority-carrier diffusion length of the injector region (6) and/or of each other. These further regions (8) float at a potential dependant on the minority-carrier injection (16) from the injector region (6) and serve to inject minority charge carries (18) into areas of the body portion (1) remote from the injector region (6) so as to modulate the conductivity of these areas of the current path (20). The floating regions (8) may be located within the spread of a depletion layer (30) from a reverse-biased p-n junction (2) to increase the breakdown voltage of the junction (2). The body portion (1) may be, e.g., a MOST drain drift region or a bipolar transistor collector region or a thyristor base region.
    • 半导体器件,例如 横向DMOS晶体管或双极晶体管具有延伸穿过一种导电类型的高电阻率主体部分(1)的主电流路径(20)。 在电流路径(20)附近在主体部分(1)中设置可以具有相反导电类型的少数载流子注入器区域(6),并施加正向偏压以注入少数电荷载流子 16),其特征在于主体部分(1)中的相反导电类型,以调节电流路径(20)的导电性。 根据本发明,相反导电类型的一个或多个另外的区域(8)位于电流路径(20)附近的主体部分(1)的部分中,并且位于主体部分(1)的少数载流子扩散长度内 注射器区域(6)和/或彼此。 这些另外的区域(8)浮动在取决于少数载流子注入(16)的注入区域(6)的电位,并且用于将少数电荷载体(18)注入远离注射器的身体部分(1)的区域 区域(6),以便调制电流路径(20)的这些区域的电导率。 浮动区域(8)可以位于来自反向偏置p-n结(2)的耗尽层(30)的扩展内,以增加结(2)的击穿电压。 主体部分(1)可以是例如MOST漏极漂移区域或双极晶体管集电极区域或晶闸管基极区域。