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31. 发明授权

US5544118A Flash EEPROM system cell array with defect management including an error correction scheme 失效
标题翻译：具有缺陷管理的闪存EEPROM系统单元阵列包括纠错方案
公开(公告)号：US5544118A
公开(公告)日：1996-08-06
申请号：US400034
申请日：1995-03-07
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34 , G11C29/00 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788 , G11C7/00
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/349 , G11C16/3495 , G11C29/765 , G11C29/82 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L29/7881 , H01L29/7885 , G11C2211/5613 , G11C2211/5631 , G11C2211/5634 , G11C2211/5644 , G11C29/00
摘要： A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occured. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferably as part of the blocks themselves, in order to maintain an endurance history of cells within the block. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
摘要翻译：由电可编程只读存储器（EPROM）或闪存电可擦除和可编程只读存储器（EEPROM）单元组成的存储器系统。智能编程技术允许每个存储器单元存储比通常的一位信息。通过建立单元被编程的两个以上不同的阈值状态，多个位被存储在单元中。在其编程期间，一系列增加电压的脉冲被施加到每个寻址的存储器单元，在脉冲之间读取单元的状态。脉冲在所寻址的单元达到其期望状态时终止，或达到预设的最大脉冲数。智能擦除算法可延长存储单元的使用寿命。一系列脉冲也被施加到被擦除的单元块，在脉冲之间读取至少一个单元的样本数的状态。当读取的单元被确定为已经达到完全擦除状态或者已经发生了许多其他条件中的一种时，停止擦除过程。保存快闪EEPROM单元块所经历的擦除周期数的单独记录，优选地作为块本身的一部分，以便保持块内的单元的耐久性历史。使用这些各种特征提供了具有非常高的存储密度和长寿命的存储器，使得其作为固态存储器代替计算机系统中的磁盘存储装置是特别有用的。

32. 发明授权

US5497354A Bit map addressing schemes for flash memory 失效
公开(公告)号：US5497354A
公开(公告)日：1996-03-05
申请号：US253902
申请日：1994-06-02
申请人： Sherif Sweha , Mark E. Bauer
发明人： Sherif Sweha , Mark E. Bauer
IPC分类号： G11C16/06 , G11C8/00 , G11C11/56 , G11C16/02
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/08 , G11C2211/5631 , G11C2211/5632 , G11C2211/5642 , G11C8/00
摘要： Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

33. 发明申请

US20190115083A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20190115083A1
公开(公告)日：2019-04-18
申请号：US15987488
申请日：2018-05-23
申请人： SK hynix Inc.
发明人： Dong Uk LEE , Jae Hyuk BANG
IPC分类号： G11C16/26 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/349 , G11C29/021 , G11C29/42 , G11C2211/5631
摘要： In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.

34. 发明授权

US08873285B2 Simultaneous multi-level binary search in non-volatile storage 有权
标题翻译：在非易失性存储中同时进行多级二进制搜索
公开(公告)号：US08873285B2
公开(公告)日：2014-10-28
申请号：US13937983
申请日：2013-07-09
申请人： SanDisk IL Ltd.
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C11/34 , G11C16/34 , G11C11/56 , G11C16/04
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time. A binary search may be performed.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。可以执行二进制搜索。

35. 发明申请

US20140071761A1 NON-VOLATILE STORAGE WITH JOINT HARD BIT AND SOFT BIT READING 审中-公开
标题翻译：非易失性存储，具有接合硬点和软位读取
公开(公告)号：US20140071761A1
公开(公告)日：2014-03-13
申请号：US13743502
申请日：2013-01-17
申请人： SANDISK TECHNOLOGIES INC.
发明人： Eran Sharon , Idan Alrod , Yan Li , Yee Lih Koh , Tien-Chien Kuo
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G06F11/1012 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C2211/5624 , G11C2211/5631 , G11C2211/5632
摘要： A system is disclosed for reading hard bit information and soft bit information from non-volatile storage. Some of the hard bit information and/or soft bit information is read concurrently by using different bit line voltages, different integration times, different sense levels within the sense amplifiers, or other techniques. A method is disclosed for determining the hard bits and soft bits in real time based on sensed hard bit information and soft bit information.
摘要翻译：公开了用于从非易失性存储器读取硬比特信息和软比特信息的系统。一些硬比特信息和/或软比特信息通过使用不同的位线电压，不同的积分时间，读出放大器内的不同感测电平或其他技术同时读出。公开了一种基于感测的硬比特信息和软比特信息来实时确定硬比特和软比特的方法。

36. 发明授权

US08482955B2 Resistive memory sensing methods and devices 有权
标题翻译：电阻式记忆感测方法和装置
公开(公告)号：US08482955B2
公开(公告)日：2013-07-09
申请号：US13035193
申请日：2011-02-25
申请人： Adam D. Johnson
发明人： Adam D. Johnson
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C11/1693 , G11C11/56 , G11C13/0002 , G11C13/0007 , G11C13/0061 , G11C2211/5631 , G11C2211/5642
摘要： The present disclosure includes resistive memory sensing methods and devices. One such method includes performing a voltage based multiple pass sensing operation on a group of cells coupled to a selected conductive line of an array of resistive memory cells. The voltage based multiple pass sensing operation can include providing an indication of those cells of the group that conduct at least a threshold amount of current responsive to one of a number of different sense voltages successively applied to the selected conductive line during each of a corresponding number of the multiple passes, and for each successive pass of the multiple passes, disabling data lines corresponding to those cells determined to have conducted the threshold amount of current in association with a previous one of the multiple passes.
摘要翻译：本公开包括电阻式存储器感测方法和装置。一种这样的方法包括对耦合到电阻存储器单元阵列的所选导线的一组单元执行基于电压的多通道感测操作。基于电压的多通道感测操作可以包括提供响应于在每个相应数字中连续施加到所选导线的多个不同感测电压中的一个传导至少阈值量的电流的组的指示并且对于多个遍的每个连续通过，禁用与被确定为已经进行了多次通过中的先前一次的阈值电流量的那些单元相对应的数据线。

37. 发明授权

US07623370B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07623370B2
公开(公告)日：2009-11-24
申请号：US11761823
申请日：2007-06-12
申请人： Haruki Toda , Koichi Kubo
发明人： Haruki Toda , Koichi Kubo
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/0092 , G11C2211/5622 , G11C2211/5631 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/147
摘要： A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other, and memory cells disposed between the first and second wiring lines wherein the memory cell includes, a variable resistance element for storing as information a resistance value and a Schottky diode connected in series to the variable resistance element. The variable resistance element has a recording layer composed of a composite compound containing at least two types of cation elements, at least one type of the cation element being a transition element having “d”-orbit, in which electrons are incompletely filled, the shortest distance between adjacent cation elements being 0.32 nm or less.
摘要翻译：一种电阻变化存储装置，包括：基板，形成在所述基板上方彼此绝缘的第一和第二布线;以及设置在所述第一和第二布线之间的存储单元，其中所述存储单元包括：可变电阻元件，用于存储为信息电阻值和与可变电阻元件串联连接的肖特基二极管。可变电阻元件具有由包含至少两种阳离子元素的复合化合物构成的记录层，至少一种阳离子元素是具有“d” - 轨道的过渡元素，其中电子未完全填充，最短相邻阳离子元素之间的距离为0.32nm以下。

38. 发明申请

US20090135646A1 OPERATION SEQUENCE AND COMMANDS FOR MEASURING THRESHOLD VOLTAGE DISTRIBUTION IN MEMORY 有权
标题翻译：用于测量存储器中阈值电压分配的操作顺序和命令
公开(公告)号：US20090135646A1
公开(公告)日：2009-05-28
申请号：US11945120
申请日：2007-11-26
申请人： Mark Murin , Mark Shlick , Menahem Lasser , Cuong Trinh
发明人： Mark Murin , Mark Shlick , Menahem Lasser , Cuong Trinh
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C2211/5631 , G11C2211/5634
摘要： A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.
摘要翻译：存储器件产生一个或多个读取参考电压，而不是明确地提供来自外部主机控制器的每个读取参考电压。该技术涉及向存储器件提供命令，其使得存储器件使用不同于先前读取中使用的参考电压的参考电压来读取一组存储元件，其中新的读取参考值不是明确的设置在存储设备外面。在一个实现中，存储器件被提供有初始参考电压和用于产生附加参考电压的步长。该技术可以用于例如确定一组存储元件的阈值电压分布。在这种情况下，可以对与该组存储元件相关联的字线施加电压扫描，并且可以基于导电存储元件的数量获得的数据。

39. 发明授权

US07529130B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07529130B2
公开(公告)日：2009-05-05
申请号：US11389252
申请日：2006-03-27
申请人： Haruki Toda
发明人： Haruki Toda
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/0483 , G11C16/28 , G11C2211/5631 , G11C2211/5634
摘要： A semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; and a sense amplifier circuit configured to read out data of the memory cell array, wherein a plurality of information cells, in each of which one of M(M≧2) physical quantity levels is written, and at least one reference cell, in which a reference physical quantity level is written, are defined in the memory cell array, and the sense amplifier circuit detects a cell current difference between the information cell and the reference cell selected simultaneously in the memory cell array to sense data defined by the M physical quantity levels of the information cell.
摘要翻译：半导体存储器件包括：具有布置在其中的电可重写和非易失性存储单元的存储单元阵列; 以及读出放大器电路，被配置为读出存储单元阵列的数据，其中写入了M（M> = 2）个物理量级别中的一个的多个信息单元和至少一个参考单元，在存储单元阵列中定义参考物理量级别，并且读出放大器电路检测在存储单元阵列中同时选择的信息单元和参考单元之间的单元电流差，以感测由M个物理信息单元的数量级别。

40. 发明授权

US07447094B2 Method for power-saving multi-pass sensing in non-volatile memory 有权
标题翻译：非易失性存储器中省电多通道感测的方法
公开(公告)号：US07447094B2
公开(公告)日：2008-11-04
申请号：US11322427
申请日：2005-12-29
申请人： Shou-Chang Tsao , Yan Li
发明人： Shou-Chang Tsao , Yan Li
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C7/08 , G11C7/12 , G11C16/0483 , G11C16/24 , G11C16/28 , G11C2207/005 , G11C2211/5631
摘要： Power-saving techniques are employed in sensing a group of non-volatile memory cells in parallel. One technique is that the coupling of the memory cells to their bit lines is delayed during a precharge operation in order to reduce the cells'currents working against the precharge. Another technique is that a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will still be able to be detected in a subsequent pass.
摘要翻译：同时采用省电技术来感测一组非易失性存储单元。一种技术是在预充电操作期间，存储器单元与其位线的耦合被延迟，以便减小单元电流对预充电的作用。另一种技术是通过在多遍感测操作中预先启动感测来最大限度地减少功耗的预充电周期。作为过早感测的结果，未检测到的高电流电流仍然能够在随后的通过中被检测。

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