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31. 发明申请

US20160357698A1 NVM Express Controller for Remote Access of Memory and I/O Over Ethernet-Type Networks 审中-公开
公开(公告)号：US20160357698A1
公开(公告)日：2016-12-08
申请号：US15242299
申请日：2016-08-19
申请人： CNEX Labs, Inc.
发明人： Yiren Ronnie Huang
IPC分类号： G06F13/40 , H04L29/12 , H04L29/08 , G06F13/42
CPC分类号： G06F13/4068 , G06F11/201 , G06F11/3027 , G06F11/349 , G06F12/0835 , G06F13/00 , G06F13/161 , G06F13/1684 , G06F13/42 , G06F13/4221 , G06F15/17337 , G06F16/10 , G06F2213/0026 , H04L12/40176 , H04L61/1582 , H04L61/6022 , H04L67/1097
摘要： A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame.

32. 发明申请

US20160328340A1 MEMORY SUBSYSTEM AND COMPUTER SYSTEM 审中-公开
标题翻译：内存子系统和计算机系统
公开(公告)号：US20160328340A1
公开(公告)日：2016-11-10
申请号：US15215018
申请日：2016-07-20
申请人： International Business Machines Corporation
发明人： Norio Fujita , Masahiro Hori , Masahiro Murakami , Junka Okazawa
IPC分类号： G06F13/16 , G06F13/40 , G06F3/06
CPC分类号： G06F13/1689 , G06F1/324 , G06F3/0625 , G06F3/0653 , G06F3/0673 , G06F11/3027 , G06F13/161 , G06F13/364 , G06F13/4068 , G06F13/4282 , Y02D10/14 , Y02D10/151
摘要： A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.
摘要翻译：一种方法，其包括通过计数CPU访问请求的数量和除CPU访问请求之外的多个请求来估计从CPU到存储器子系统的访问请求频率，其中CPU经由系统总线连接到存储器子系统，并且存储器子系统包括连接到系统总线的存储器控制器和DDR存储器，其包括具有存储在寄存器中的预定阈值的估计的访问请求频率，产生时钟门信号以响应于存储器控制器的操作时钟来抽取将估计的访问请求频率与预定阈值进行比较的结果，生成虚拟周期信号以将从存储器控制器输出的信号数据的定时延迟到系统总线，以及生成时钟使能信号以抽取 DDR内存

33. 发明申请

US20160328000A1 MEMORY SUBSYSTEM AND COMPUTER SYSTEM 审中-公开
标题翻译：内存子系统和计算机系统
公开(公告)号：US20160328000A1
公开(公告)日：2016-11-10
申请号：US15215105
申请日：2016-07-20
申请人： International Business Machines Corporation
发明人： Norio Fujita , Masahiro Hori , Masahiro Murakami , Junka Okazawa
IPC分类号： G06F1/32 , G06F11/30 , G06F13/16 , G06F13/364 , G06F13/42
CPC分类号： G06F13/1689 , G06F1/324 , G06F3/0625 , G06F3/0653 , G06F3/0673 , G06F11/3027 , G06F13/161 , G06F13/364 , G06F13/4068 , G06F13/4282 , Y02D10/14 , Y02D10/151
摘要： A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.
摘要翻译：一种计算机系统，包括经由系统总线连接的CPU和存储子系统以进行通信，其中所述存储器子系统包括连接到所述系统总线的存储器控制器，所述计算机系统包括用于对多个访问进行计数的上/下计数器请求和除访问请求之外的多个请求，比较器，用于将上/下计数器的计数与存储在寄存器中的预定阈值进行比较;以及时钟门电路，用于产生时钟门信号以抽取存储器控制器响应比较器的比较结果。

34. 发明授权

US09477619B2 Programmable latency count to achieve higher memory bandwidth 有权
标题翻译：可编程延迟计数，以实现更高的内存带宽
公开(公告)号：US09477619B2
公开(公告)日：2016-10-25
申请号：US13913909
申请日：2013-06-10
申请人： Cypress Semiconductor Corporation
发明人： Qamrul Hasan , Dawn M. Hopper , Clifford Alan Zitlaw
IPC分类号： G06F13/40 , G06F13/16 , G06F13/42 , G06F3/06
CPC分类号： G06F13/1689 , G06F3/0613 , G06F3/0655 , G06F3/0683 , G06F13/161 , G06F13/4243 , G06F13/4291
摘要： Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device.
摘要翻译：这里公开了用于在访问多个存储器设备时增加存储器带宽的系统，方法和/或计算机程序产品实施例。实施例通过至少一个处理器执行第一读取操作，以在第一存储器设备的访问时间之后从第一存储器设备读取数据。该实施例还包括由至少一个处理器执行第二读取操作，以在第二存储器设备的访问时间之后从第二存储器设备读取数据。第二存储设备的访问时间与第一存储设备的访问时间基本相同或更长，加上从第一存储设备读取数据所花费的时间。

35. 发明申请

US20160306756A1 MEMORY SYSTEM, MEMORY MODULE AND METHOD TO BACKUP AND RESTORE SYSTEM USING COMMAND ADDRESS LATENCY 有权
标题翻译：存储器系统，存储器模块和使用命令地址延迟备份和恢复系统的方法
公开(公告)号：US20160306756A1
公开(公告)日：2016-10-20
申请号：US14845870
申请日：2015-09-04
申请人： SK hynix Inc.
发明人： Hyun-Ju YOON
IPC分类号： G06F13/16 , G11C15/04 , G11C8/18 , G06F13/40
CPC分类号： G06F13/161 , G06F13/1657 , G06F13/1694 , G06F13/404 , G11C8/18 , G11C15/046
摘要： A memory system having a plurality of memory devices includes a controller for separately accessing the memory devices. The memory system includes a data bus for transferring data, a control bus for transferring a command and address CAL, and first and second memory devices coupled to the data bus and the control bus. The controller controls the first and second memory devices through the data bus and the control bus, wherein the first and second memory devices have different values of the CAL, and wherein a difference of the CAL values is greater than or equal to a RAS to CAS delay time tRCD.
摘要翻译：具有多个存储器件的存储器系统包括用于分别存取存储器件的控制器。存储器系统包括用于传送数据的数据总线，用于传送命令和地址CAL的控制总线以及耦合到数据总线和控制总线的第一和第二存储器件。控制器通过数据总线和控制总线控制第一和第二存储器件，其中第一和第二存储器件具有不同的CAL值，并且其中CAL值的差值大于或等于RAS至CAS 延迟时间tRCD。

36. 发明授权

US09471517B1 Memory system, memory module and method to backup and restore system using command address latency 有权
标题翻译：内存系统，内存模块和使用命令地址延迟备份和恢复系统的方法
公开(公告)号：US09471517B1
公开(公告)日：2016-10-18
申请号：US14845870
申请日：2015-09-04
申请人： SK hynix Inc.
发明人： Hyun-Ju Yoon
IPC分类号： G06F13/16 , G06F13/40 , G11C15/04 , G11C8/18
CPC分类号： G06F13/161 , G06F13/1657 , G06F13/1694 , G06F13/404 , G11C8/18 , G11C15/046
摘要： A memory system having a plurality of memory devices includes a controller for separately accessing the memory devices. The memory system includes a data bus for transferring data, a control bus for transferring a command and address CAL, and first and second memory devices coupled to the data bus and the control bus. The controller controls the first and second memory devices through the data bus and the control bus, wherein the first and second memory devices have different values of the CAL, and wherein a difference of the CAL values is greater than or equal to a RAS to CAS delay time tRCD.
摘要翻译：具有多个存储器件的存储器系统包括用于分别存取存储器件的控制器。存储器系统包括用于传送数据的数据总线，用于传送命令和地址CAL的控制总线以及耦合到数据总线和控制总线的第一和第二存储器件。控制器通过数据总线和控制总线控制第一和第二存储器件，其中第一和第二存储器件具有不同的CAL值，并且其中CAL值的差值大于或等于RAS到CAS 延迟时间tRCD。

37. 发明授权

US09465539B2 Operation management in a memory device 有权
标题翻译：存储设备中的操作管理
公开(公告)号：US09465539B2
公开(公告)日：2016-10-11
申请号：US14943113
申请日：2015-11-17
申请人： MICRON TECHNOLOGY, INC.
发明人： Anthony R. Cabrera , Nicholas Hendrickson , Robert Melcher
IPC分类号： G06F12/00 , G06F3/06 , G06F12/02
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/161 , G06F2212/7205
摘要： Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation.
摘要翻译：操作存储器件的方法包括执行具有相关定时要求的第一存储器操作; 在完成第一存储器操作之后，确定第一存储器操作的完成和其相关的定时要求的到期之间的定时裕度是否超过执行第二存储器操作的特定部分的时间长度; 以及如果确定第一存储器操作的完成与其相关联的定时要求的期满之间的时间裕度超过了长度，则在完成第一存储器操作和其关联的定时要求期满之后执行第二存储器操作的特定部分的时间来执行第二存储器操作的特定部分。

38. 发明申请

US20160292092A1 Memory Bus Management 有权
标题翻译：内存总线管理
公开(公告)号：US20160292092A1
公开(公告)日：2016-10-06
申请号：US14675353
申请日：2015-03-31
申请人： SanDisk Technologies Inc.
发明人： Lee Gavens , Daniel Lee , Meiqing He , Christopher Dinh
IPC分类号： G06F13/16 , G06F3/06 , G06F13/40
CPC分类号： G06F13/1642 , G06F3/0604 , G06F3/0629 , G06F3/0688 , G06F13/161 , G06F13/4068 , Y02D10/14 , Y02D10/151
摘要： A method of managing a memory bus includes identifying sub-operations required for execution of commands, maintaining a list of released sub-operations containing only released unexecuted sub-operations directed to individual dies that are identified as available, accessing the dies until the list is empty, subsequently, polling to identify dies that are available, and subsequently resuming accessing the dies by executing only sub-operations from the list until the list is empty.
摘要翻译：管理存储器总线的方法包括识别执行命令所需的子操作，维护仅包含被识别为可用的单个管芯的已释放的未执行子操作的释放子操作的列表，访问管芯直到列表为空，随后，轮询以识别可用的模具，并且随后通过仅执行列表中的子操作恢复访问模具，直到列表为空。

39. 发明申请

US20160292091A1 PACKET PROCESSING SYSTEM, METHOD AND DEVICE UTILIZING A PORT CLIENT CHAIN 有权
标题翻译：分组处理系统，使用端口客户端链的方法和设备
公开(公告)号：US20160292091A1
公开(公告)日：2016-10-06
申请号：US14673828
申请日：2015-03-30
申请人： XPLIANT, Inc.
发明人： Enrique Musoll , Tsahi Daniel
IPC分类号： G06F13/16 , G06F13/40
CPC分类号： G06F13/1663 , G06F13/161 , G06F13/1673 , G06F13/4022 , H04L45/126 , H04L49/9005
摘要： A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.
摘要翻译：具有多个分级客户机中的每一个的分组处理系统和经由多个主接口串行通信地耦合在一起的分组存储器仲裁器，从而形成单向客户端链。然后，该链可以被所有层级客户端利用来将分组数据写入或从分组存储器读取分组数据。

40. 发明申请

US20160266804A1 MEMORY DEVICE 审中-公开
标题翻译：内存设备
公开(公告)号：US20160266804A1
公开(公告)日：2016-09-15
申请号：US14852398
申请日：2015-09-11
申请人： Naoki SHIMIZU
发明人： Naoki SHIMIZU
IPC分类号： G06F3/06
CPC分类号： G11C11/1673 , G06F13/161 , G11C11/1693 , G11C13/004 , G11C13/0061
摘要： According to one embodiment, a memory device includes a memory area; and a control circuit, in response to a first command, configured to read out data from the memory area without outputting the data to a data line, subsequently, in response to a second command, configured to output the data to the data line, if the first command is not received after receiving an active command, in response to the second command, configured to output the data read out from the memory area to the data line.
摘要翻译：根据一个实施例，存储器装置包括存储区域; 以及控制电路，响应于第一命令，被配置为从存储器区域读出数据而不将数据输出到数据线，随后响应于第二命令将数据输出到数据线，如果在接收到有效命令之后，响应于第二命令，第一命令被配置为将从存储器区域读出的数据输出到数据线。

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