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31. 发明授权

US5777601A System and method for generating video in a computer system 失效
标题翻译：用于在计算机系统中生成视频的系统和方法
公开(公告)号：US5777601A
公开(公告)日：1998-07-07
申请号：US687274
申请日：1996-07-25
申请人： David C. Baker , Daniel P. Mulligan , Eric J. Schell
发明人： David C. Baker , Daniel P. Mulligan , Eric J. Schell
IPC分类号： H04N11/20 , G09G5/00 , G09G5/06 , G09G5/39 , G09G5/393 , G09G5/395 , H04N7/01 , H04N9/64 , H04N11/14 , H04N11/16 , G09G5/02
CPC分类号： H04N9/641 , G09G5/39 , G09G2310/04 , G09G2340/02 , G09G2340/125 , G09G5/06 , G09G5/393 , H04N11/14 , H04N11/16
摘要： A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided in a display memory and is used for modulation of the chrominance components. The modulated components are then combined to form digital composite video pixel data which may be stored in a frame buffer in the display memory. Video control information is precalculated and stored in the display memory in advance. The digital composite video pixel data and video control information are then recovered from the display memory to produce a formatted stream of video data. The architecture of this system greatly reduces hardware complexity and bandwidth requirements. In addition, the process may be controlled by a media stream controller which is also adapted for audio and graphics processing. This allows the display memory and various other components to be shared by multiple media subsystems.
摘要翻译：一种用于在计算机中产生复合视频信号的系统和方法。数字像素数据可以由软件处理以形成分量视频像素数据，其可以包括亮度和色度分量。在显示存储器中提供色度查找表，并用于色度分量的调制。然后将调制的分量组合以形成可以存储在显示存储器中的帧缓冲器中的数字复合视频像素数据。视频控制信息被预先计算并预先存储在显示存储器中。然后从显示存储器恢复数字复合视频像素数据和视频控制信息，以产生格式化的视频数据流。该系统的架构大大降低了硬件复杂性和带宽要求。此外，该过程可以由也适用于音频和图形处理的媒体流控制器来控制。这允许显示存储器和各种其他组件由多个媒体子系统共享。

32. 发明授权

US5764074A System for, and method of, minimizing noise in an integrated circuit chip 失效
标题翻译：用于集成电路芯片中噪声最小化的系统和方法
公开(公告)号：US5764074A
公开(公告)日：1998-06-09
申请号：US715234
申请日：1996-09-18
申请人： Michael D. Wykes , Michael J. Brunolli
发明人： Michael D. Wykes , Michael J. Brunolli
IPC分类号： H03M1/06 , H03H17/02 , H03K3/013 , H03K17/16 , H03K19/003
CPC分类号： H03K19/00346
摘要： The noise from the effects of currents through distributed capacitances between electrical circuitry on an integrated circuit chip and the chip substrate is minimized, especially for analog circuitry mixed on the chip with digital circuitry. The invention separates a plurality of bits in each digital word into a plurality (e.g. 2) of segments. A first register off the chip latches the first bits in each word with a first clock signal. A second register off the chip latches the second bits in each word with a second clock signal delayed from the first clock signal. The first register bits are latched on the chip with the first clock signal by a third register. The delayed second register bits are latched on the chip by a fourth register with the second clock signal or with a delayed first clock signal having the same delay as the second clock signal. Substrate ties for the third and fourth registers may be connected to at least one, preferably a plurality, of bonding pads on the chip. The bits from the third and fourth registers may be combined on the chip into a single word. Alternatively, the bits from the third register may be delayed on the chip by the delay of the second clock signal and combined with the bits from the fourth register. In another alternative, the combined signals may be re-registered on the chip in a fifth register in accordance with a clock signal having the delay of the second clock signal.
摘要翻译：通过集成电路芯片上的电路与芯片基板之间的分布电容的电流影响的噪声最小化，特别是对于使用数字电路混合在芯片上的模拟电路。本发明将每个数字字中的多个位分成多个（例如2个）段。芯片上的第一个寄存器用第一个时钟信号锁存每个字中的第一个位。芯片上的第二个寄存器将从第一个时钟信号延迟的第二个时钟信号锁存每个字中的第二个位。第一个寄存器位由第三个寄存器用第一个时钟信号锁存在芯片上。延迟的第二寄存器位由具有第二时钟信号的第四寄存器或具有与第二时钟信号相同的延迟的延迟的第一时钟信号在芯片上锁存。用于第三和第四寄存器的衬底可以连接到芯片上的至少一个，优选多个接合焊盘。来自第三和第四寄存器的位可以在芯片上组合成单个字。或者，来自第三寄存器的位可以在芯片上延迟第二时钟信号的延迟并与来自第四寄存器的位组合。在另一替代方案中，可以根据具有第二时钟信号的延迟的时钟信号在第五寄存器中的芯片上重新注册组合的信号。

33. 发明授权

US5761208A Expansible high speed digital multiplexer 失效
标题翻译：可扩展高速数字多路复用器
公开(公告)号：US5761208A
公开(公告)日：1998-06-02
申请号：US725733
申请日：1996-10-04
申请人： John J. Muramatsu
发明人： John J. Muramatsu
IPC分类号： H03K5/00 , G06F13/40 , H03K17/00 , H03K17/62 , H04J3/00
CPC分类号： H03K17/002 , G06F13/4022 , H03K17/6228 , H03K17/6264
摘要： A multiplexer, preferably on an integrated circuit chip, receives a plurality of buses each having a plurality of lines responsive to binary indications and passes the binary indications in the lines of a particular one of the buses. The multiplexer includes a plurality of circuit blocks each responsive to the binary indications in the lines of an individual one of the buses. Each block has a plurality of recursive circuits each having first and second stages. The second stages of the recursive circuits in an individual one of the circuit blocks receive an individual one of a plurality of control indications at a first side of the block to activate the first stages in such recursive circuits. The first stage in each recursive circuit in each individual circuit block receives at a second side of the block the binary indications in an individual line in an individual one of the buses to obtain a signal from such first stage in accordance with such binary indication upon the activation of such first stage. The output lines of the same binary significance in the different circuit blocks are connected in an OR relationship. Each output circuit in a plurality is responsive to the signals in the OR relationship of an individual binary significance from the recursive circuit in the activated block to provide output signals from the multiplexer. The multiplexer accordingly provides a recursive and expansible, arrangement for passing signals at each instant from a selected bus without any wire crossovers.
摘要翻译：优选地在集成电路芯片上的多路复用器接收多个总线，每个总线具有响应于二进制指示的多个线，并且通过特定一个总线的线路中的二进制指示。多路复用器包括多个电路块，每个电路块响应于单个总线中的二线指示。每个块具有各自具有第一和第二阶段的多个递归电路。各个电路块中的递归电路的第二级在块的第一侧接收多个控制指示中的单独一个，以激活这些递归电路中的第一级。每个单独电路块中的每个递归电路中的第一阶段在该块的第二侧处接收单独一条总线中的单独线路中的二进制指示，以便根据这样的二进制指示从这种第一级获得信号激活这样的第一阶段。在不同电路块中具有相同二进制含义的输出线以OR关系连接。多个中的每个输出电路响应来自激活块中的递归电路的与二进制有关的OR关系的信号，以提供来自多路复用器的输出信号。因此，多路复用器提供递归和可扩展的布置，用于在每个时刻从选定的总线传递信号，而无需任何线分频。

34. 发明授权

US5521539A Delay line providing an adjustable delay 失效
标题翻译：延迟线提供可调延迟
公开(公告)号：US5521539A
公开(公告)日：1996-05-28
申请号：US986723
申请日：1992-12-08
申请人： Stuart B. Molin
发明人： Stuart B. Molin
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： First and second complementary input voltages control current flow through first and second switches (e.g. semiconductor devices) each respectively connected in first and second control circuits with a first constant current source. When the input voltages change, current starts to increase through one control circuit to produce increases in the voltage drop across an impedance (e.g. resistor) in such circuit. When a particular voltage difference is produced between the impedance voltage and an adjustable biasing voltage, a third switch (e.g. semiconductor device) closes to produce a first resultant voltage. The resultant delay in the third switch closure is dependent upon the adjustable magnitude of the biasing voltage. As the voltage increases across the impedance in the one control circuit, the voltage decreases across an impedance in the other control circuit, causing a second resultant voltage to be produced at a fourth switch (e.g. semiconductor device). The resultant voltages are respectively introduced to fifth and sixth switches (e.g. semiconductor devices) each connected in a circuit with an individual one of second and third constant current sources. When the resultant voltages change, the particular one of the fifth and sixth switches receiving an increase in current passes a portion of this current through the associated current source and another portion of this current through a coupling member and the other current source. This delays the state of non-conductivity of the switch connected to the other current source. Output voltages further delayed from the input voltages are accordingly obtained from the fifth and sixth switches.
摘要翻译：第一和第二互补输入电压控制电流流过第一和第二开关（例如半导体器件），每个开关和第二开关分别连接在第一和第二控制电路中的第一恒定电流源。当输入电压变化时，电流通过一个控制电路开始增加，以产生在这种电路中的阻抗（例如电阻）上的电压降的增加。当在阻抗电压和可调偏置电压之间产生特定的电压差时，第三开关（例如半导体器件）闭合以产生第一合成电压。第三个开关闭合的结果延迟取决于偏置电压的可调整幅度。随着一个控制电路中的阻抗上的电压增加，电压在另一控制电路中的阻抗上减小，导致在第四开关（例如半导体器件）产生第二合成电压。所得到的电压分别被引入到第五和第六开关（例如，半导体器件），每个开关（例如半导体器件）在电路中与第二和第三恒定电流源中的一个连接。当所得到的电压变化时，接收电流增加的第五和第六开关中的特定一个使该电流的一部分通过相关联的电流源，并且该电流的另一部分通过耦合构件和另一个电流源。这延迟了连接到另一个电流源的开关的非导电性状态。因此从第五和第六开关获得进一步从输入电压延迟的输出电压。

35. 发明授权

US5400056A Apparatus for and method of processing and converting binary information to corresponding analog signals 失效
标题翻译：二进制信息处理和转换为相应的模拟信号的装置和方法
公开(公告)号：US5400056A
公开(公告)日：1995-03-21
申请号：US6813
申请日：1993-01-21
申请人： Joseph H. Colles
发明人： Joseph H. Colles
IPC分类号： G09G5/02 , G09G5/395 , G09G1/28
CPC分类号： G09G5/395 , G09G5/02
摘要： In first and second modes, successive pairs of bytes, each with a suitable number (e.g. 8) of binary indications, are respectively processed in each clock cycle or clock half cycle to provide a true color. In these modes, the successive pairs of bytes may be processed in a 5,5,5, or a 5,6,5 pattern representing the primary colors for a pixel. In a third mode, the bytes may be introduced to a memory having a plurality of positions for storing individual binary combinations, which may be updated by a microprocessor, representing pseudo colors. In the third mode, a particular position in the memory is selected in accordance with the indications in each byte in each clock cycle or half cycle. In an additional mode, three successive bytes in a group may indicate the primary colors defining a true color when the fourth byte in the group provides a particular indication (e.g. 0 for all 8 binary bits). In this mode, indications in the fourth byte other than the particular indication select a particular position in the memory to represent a pseudo color. In this mode, the successive bytes may be respectively provided either in each clock cycle or clock half cycle. The binary indications representing the true color or the pseudo color in the different modes are converted to analog signals for introduction to a video monitor. In the additional mode, the indications in particular positions in the memory may be blocked from conversion to analog signals.
摘要翻译：在第一和第二模式中，在每个时钟周期或时钟半周期中分别处理连续的字节对，每个字节具有适当数量（例如8个）二进制指示，以提供真实颜色。在这些模式中，连续的字节对可以在表示像素的原色的5,5,5或5,6,5图案中进行处理。在第三模式中，字节可以被引入具有多个位置的存储器，该存储器用于存储表示伪颜色的可由微处理器更新的各个二进制组合。在第三模式中，根据每个时钟周期或半周期中的每个字节的指示来选择存储器中的特定位置。在附加模式中，组中的三个连续字节可以指示当组中的第四个字节提供特定指示（例如对于所有8个二进制位为0）时定义真实颜色的主要颜色。在该模式中，除特定指示之外的第四字节中的指示选择存储器中的特定位置以表示伪颜色。在该模式中，可以在每个时钟周期或时钟半周期内分别提供连续的字节。表示不同模式中的真实颜色或伪色的二进制指示被转换为模拟信号，以引入视频监视器。在附加模式中，存储器中特定位置的指示可能被阻止转换为模拟信号。

36. 发明授权

US5338990A Regulated delay line 失效
标题翻译：调节延时线
公开(公告)号：US5338990A
公开(公告)日：1994-08-16
申请号：US019784
申请日：1993-02-19
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H03K5/00 , H03K5/13 , H03K5/159 , H03K3/01
CPC分类号： H03K5/131 , H03K2005/00097 , H03K2005/00136
摘要： Three delay lines may have common characteristics. The first delay line delays the rising edge of an input signal and a first inverter inverts this signal to provide a falling edge. A second inverter inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line in a second path with the second inverter. The signals from the two paths may be introduced to a comparator which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal. This voltage is introduced to the first and second delay lines to adjust their delay to minimize the time difference in the falling edges of the signals from these lines. This voltage is also introduced to the third delay line to adjust its delay in accordance with the adjustments in the delays in the first and second lines. In this way, the third delay line provides the same time for rising edges and falling edges in data signals introduced to the line.
摘要翻译：三条延迟线可能具有共同特征。第一延迟线延迟输入信号的上升沿，第一反相器反相该信号以提供下降沿。第二反相器反转输入信号的上升沿，产生下降沿，该下降沿与第二反相器以第二路径被引入第二延迟线。来自两个路径的信号可以被引入比较器，该比较器产生具有逻辑电平的控制信号，该逻辑电平取决于两个路径中的信号的下降沿的相对时间。例如，当下降沿首先在第一路径中发生时，控制信号可以具有第一逻辑电平，并且当下降沿首先在第二路径中发生时，控制信号可能具有第二逻辑电平。来自电荷泵的电压根据控制信号的逻辑电平进行调节。该电压被引入到第一和第二延迟线以调整它们的延迟以最小化来自这些线的信号的下降沿中的时间差。该电压也被引入第三延迟线，以根据第一和第二线中的延迟的调整来调整其延迟。以这种方式，第三延迟线为引入到线路的数据信号中的上升沿和下降沿提供相同的时间。

37. 发明授权

US5130570A Constant-current integrated power supply 失效
标题翻译：恒流集成电源
公开(公告)号：US5130570A
公开(公告)日：1992-07-14
申请号：US620768
申请日：1990-12-03
申请人： Lanny L. Lewyn
发明人： Lanny L. Lewyn
IPC分类号： H02J1/00 , H02M3/07
CPC分类号： H02M3/07
摘要： A positive energizing voltage, preferably in a CMOS circuit, is converted, primarily by a pair of buffer capacitors and secondarily by a filter capacitor, to a particular negative potential. One buffer capacitor is charged through first switches by the positive voltage during the positive half cycles of a clock signal. The buffer capacitor is discharged to a load during the negative half cycles of the clock signal through a circuit including such buffer capacitor, second switches, a third switch, a reference voltage (e.g. ground) line and a line for providing a negative biasing potential. The other buffer capacitor is charged through fourth switches by the positive voltage during the negative half cycles of the clock signals. This buffer capacitor is discharged to the load during the positive half cycles of the clock signals through a circuit including such other buffer capacitor, fifth switches, the third switch, the reference voltage line and the negative potential line. The third switch has at each instant a variable state of conductivity dependent upon the magnitude of the negative biasing potential at that instant. The magnitude of the negative potential is varied in accordance with the variations in the state of conductivity of the third switch to regulate the negative potential at a particular value. The filter capacitor is charged by the negative biasing potential and is discharged to the load when the second and fifth switches are simultaneously open. This occurs for a brief interval every time that the polarity of the clock signal changes.

38. 发明授权

US4983973A Non-linear analog-to-digital converter 失效
标题翻译：非线性模数转换器
公开(公告)号：US4983973A
公开(公告)日：1991-01-08
申请号：US354864
申请日：1989-05-22
申请人： Lanny L. Lewyn
发明人： Lanny L. Lewyn
IPC分类号： H04N7/26 , H03M1/36
CPC分类号： H03M1/367 , H03M1/362
摘要： A first film disposed in a first direction on an integrated circuit chip and having uniformly spaced taps provides progressively increasing resistance values. A second film disposed on the chip in a direction opposite to the first direction at a position displaced in any direction from the first film may have a construction corresponding to that of the first film. First and second reference voltages may be respectively applied to the first and second ends of the first and second films. Particular taps on the first film may be connected to taps in corresponding positions on the second film with corresponding voltages. A plurality of differential comparators are provided, each with a signal input and a reference input. Each comparator reference input is connected to an individual one of the taps on the first film, but not necessarily to successive taps. The reference input connections to the taps may have a non-linear (e.g. a luminance) spacing in the first direction to provide a non-linear voltage (e.g. a luminance) relationship between such taps. For low voltages, however, the reference input connections to the taps may have a linear spacing in the first direction to provide a linear voltage relationship between such taps. An input voltage is applied to the signal input of all the comparators. Binary signals representative of the input voltage are produced by the comparator in which the input voltage is substantially equal to the reference input voltage introduced to such comparator.

39. 发明授权

US4928102A Flash analog-to-digital converter with logarithmic/linear threshold voltages 失效
标题翻译：具有对数/线性阈值电压的闪存模数转换器
公开(公告)号：US4928102A
公开(公告)日：1990-05-22
申请号：US231100
申请日：1988-08-11
申请人： Henry S. Katzenstein
发明人： Henry S. Katzenstein
IPC分类号： H01L27/04 , H01L21/822 , H03M1/36
CPC分类号： H03M1/365 , H03M1/367
摘要： A plurality of equally spaced terminals may be disposed at a side edge of a substantially uniformly resistive thin film. A reference potential (e.g. ground) may be applied to the second side of the film. An energizing voltage may be applied at the juncture between the first side edge and a particular one of the top and bottom edges of the film. In this way, the successive terminals receive voltages with a logarithmic relationship relative to the terminal positions. When a linear relationship of voltages is desired at successive terminals in a low range, no reference potential is applied to the second side edge of the thin film. Instead, the other one of the top and bottom edges may receive the reference voltage. Alternatively no reference voltage may be applied and terminals indicating the linear voltages may be disposed at such other edge. Each of a plurality of comparators providing an output indicative of the input voltage receives an input voltage and the voltage at an individual one of the successive terminals. The voltages in the logarithmic portion of the thin film may be calibrated by a circuit including a capacitance to indicate voltage deviations from the logarithmic relationship. The successive terminal voltages in the linear portion of the film may be calibrated by the capacitance circuit and a constant current source to indicate voltage deviations from the linear relationship.

40. 发明授权

US4875046A Centroiding algorithm for networks used in A/D and D/A converters 失效
标题翻译：用于A / D和D / A转换器的网络的中心算法
公开(公告)号：US4875046A
公开(公告)日：1989-10-17
申请号：US884472
申请日：1986-07-11
申请人： Lanny L. Lewyn
发明人： Lanny L. Lewyn
IPC分类号： H03M1/02 , H03M1/00 , H03M1/74
CPC分类号： H03M1/068 , H03M1/76
摘要： A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values. This invention compensates for such errors. The invention includes a second converter disposed on the chip with a construction substantially identical to the first converter and rotated on the chip substantially 180.degree. relative to the first converter. In this way, pairs of output members of the same binary significance may have, on the average, a median position in a first direction. Individual ones of the output members in the second plurality may have the same positioning, in a second direction co-ordinate with the first direction, as corresponding ones of the output members in the first plurality.
摘要翻译：数模转换器包括解码网络和诸如电容器的多个输出构件。解码网络接收分别具有分别编码二进制“1”和二进制“0”的逻辑电平的多个二进制信号，并分别编码单独加权的有效值的二进制值并累加地编码模拟值。网络解码二进制信号的逻辑电平，并根据这种解码激活输出成员。当由二进制信号的逻辑电平编码的模拟值增加时，先前在多个激活的输出部件保持激活，并且多个其他输出部件被激活。解码网络和输出部件设置在集成电路芯片上。取决于它们在芯片上的定位，输出构件具有不同的特性，这导致在模拟信号中产生误差，特别是在低模拟值时。本发明补偿了这种错误。本发明包括设置在芯片上的第二转换器，其具有与第一转换器基本相同的结构，并且相对于第一转换器在芯片上大致旋转180度。以这种方式，具有相同二进制含义的输出成员对平均可以具有第一方向上的中位数。第二多个中的输出构件中的各个可以在与第一方向相协调的第二方向上具有与第一多个中的输出构件中的对应的相同的定位。

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