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1. 发明授权

US09319038B2 Glitch free input transition detector 有权
标题翻译：无毛刺输入转换检测器
公开(公告)号：US09319038B2
公开(公告)日：2016-04-19
申请号：US14519071
申请日：2014-10-20
申请人： Integrated Silicon Solution, Inc.
发明人： Seong Jun Jang
IPC分类号： G01R29/02 , H03K5/1534 , H03K3/013 , G01R19/175 , H03K5/00
CPC分类号： H03K5/1534 , G01R19/175 , H03K3/013 , H03K2005/00136 , H03K2005/00293
摘要： A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.
摘要翻译：用于检测输入信号上的信号转换的电路包括镜像延迟电路和输入阻塞电路，以防止信号毛刺或不需要的信号脉冲被传递到输出信号节点，从而防止信号失真被检测为有效的信号转换。输入转换检测电路产生具有一致脉冲宽度的稳定且正确的转换检测脉冲。

2. 发明授权

US08076963B2 Delay-locked loop having a delay independent of input signal duty cycle variation 有权
标题翻译：延迟锁定环路具有独立于输入信号占空比变化的延迟
公开(公告)号：US08076963B2
公开(公告)日：2011-12-13
申请号：US12559749
申请日：2009-09-15
申请人： Xuhao Huang , Xiaohong Quan
发明人： Xuhao Huang , Xiaohong Quan
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03K5/13 , H03K5/133 , H03K5/1565 , H03K2005/00136
摘要： A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.
摘要翻译：延迟锁定环（DLL）使用延迟线将第一信号延迟“延迟时间”，从而产生第二信号。电容器以从第一信号的第一边缘开始的第一速率充电并持续到第二信号的边沿。然后电容器以第二速率放电，直到第一信号的另一个边沿。控制回路控制延迟时间，使得电容器的充电量与电容器放电量相同。延迟时间是恒定的并且基本上与第一信号的占空比的变化无关。在一个示例中，通过相对于第一信号占空比的变化按比例改变第一速率来实现占空比失真消除。在另一示例中，第一和第二速率与第一信号的占空比无关。

3. 发明申请

US20100321065A1 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING INSULATED GATE FIELD EFFECT TRANSISTORS 失效
标题翻译：具有绝缘栅场效应晶体管的半导体集成电路
公开(公告)号：US20100321065A1
公开(公告)日：2010-12-23
申请号：US12703924
申请日：2010-02-11
申请人： Masaharu Wada , Takehiko Hojo
发明人： Masaharu Wada , Takehiko Hojo
IPC分类号： H03K19/00 , H03K19/20
CPC分类号： H03K5/1504 , G11C19/00 , G11C19/28 , H03K5/133 , H03K19/00384 , H03K2005/00136 , H03M1/502
摘要： A semiconductor integrated circuit includes a multiplexer, a signal generating circuit, a control circuit, m inverters, n two-input NOR circuits, and cascade connected n two-shift registers. The control circuit generates a control signal in the disable state in a normal operation in which the clock signal is supplied. The control circuit generates a control signal in an enable state in the other-than-normal operation in which a higher voltage source voltage is supplied while the clock signal is not supplied. The multiplexer receives the clock signal and a low-frequency signal outputted from the signal generating circuit. The multiplexer supplies the clock signal to the sequence of the inverters upon receipt of the control signal in the disable state, and supplies the low-frequency signal to the sequence of the inverters upon receipt of the control signal in the enable state.
摘要翻译：半导体集成电路包括多路复用器，信号发生电路，控制电路，m个反相器，n个双输入NOR电路和级联的n个双移位寄存器。控制电路在提供时钟信号的正常操作中产生处于禁止状态的控制信号。控制电路在不提供时钟信号的情况下，在提供较高的电压源电压的正常以外的操作中产生使能状态的控制信号。多路复用器接收时钟信号和从信号发生电路输出的低频信号。在接收到处于禁用状态的控制信号时，多路复用器将时钟信号提供给逆变器的序列，并且在使能状态下接收到控制信号时，将低频信号提供给逆变器的序列。

4. 发明申请

US20100271096A1 WAVEFORM PROCESSING CIRCUIT 失效
标题翻译：波形处理电路
公开(公告)号：US20100271096A1
公开(公告)日：2010-10-28
申请号：US12666780
申请日：2008-06-01
申请人： Fujio Kurokawa
发明人： Fujio Kurokawa
IPC分类号： H03K5/12
CPC分类号： H03K5/13 , H03K5/04 , H03K2005/00136
摘要： A rising edge or a falling edge is finely adjusted, or a dead time and a period are adjusted with high accuracy. A waveform processing circuit includes: an integration circuit 11 receiving a rectangular or substantially-rectangular pulse and outputting a gradually increasing or decreasing signal obtained by integrating the pulse signal; a reference signal output circuit 12 outputting a constant value or a varying value as a reference signal; and a comparison circuit 13 comparing the output of the integration circuit with the output of the reference signal output circuit and outputting a pulse rising or falling at a timing when the difference between the outputs varies.
摘要翻译：精细调整上升沿或下降沿，或者以高精度调整死区时间和周期。波形处理电路包括：积分电路11，其接收矩形或大致矩形的脉冲，并输出通过对脉冲信号进行积分而获得的逐渐增加或减少的信号; 参考信号输出电路12，输出常数值或变化值作为参考信号; 以及比较电路13，将积分电路的输出与参考信号输出电路的输出进行比较，并且在输出之间的差异变化时的定时输出上升或下降的脉冲。

5. 发明授权

US07667507B2 Edge-timing adjustment circuit 有权
标题翻译：边沿定时调整电路
公开(公告)号：US07667507B2
公开(公告)日：2010-02-23
申请号：US12146663
申请日：2008-06-26
申请人： Mark L. Neidengard
发明人： Mark L. Neidengard
IPC分类号： H03L7/06
CPC分类号： H03K5/133 , G06F1/12 , H03K5/135 , H03K2005/00136
摘要： According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner.
摘要翻译：根据一些实施例，提供了一种方法和系统，用于在第一时钟调整调谐器处接收时钟输入，在第二时钟调整调谐器处接收时钟输入，经由第一时钟调整调谐器输出经调谐的反相上升时钟信号，输出通过第二时钟调整调谐器调谐的倒置时钟信号，在时钟同步器处接收反相的上升时钟信号和反相的下降时钟信号，经由时钟同步器输出同步的调谐时钟信号，在第三时钟接收同步的调谐时钟信号调整调谐器，并输出调谐时钟信号。第一时钟调整调谐器和第二时钟调整调谐器提供比第三时钟调整调谐器更粗调的调整。

6. 发明申请

US20090284283A1 RATIO ASYMMETRIC INVERTERS, AND APPARATUS INCLUDING ONE OR MORE RATIO ASYMMETRIC INVERTERS 失效
标题翻译：比例不对称逆变器和装置，包括一个或多个比例的非对称逆变器
公开(公告)号：US20090284283A1
公开(公告)日：2009-11-19
申请号：US12121149
申请日：2008-05-15
申请人： Claudio Alonso Denegri
发明人： Claudio Alonso Denegri
IPC分类号： H03K19/20 , H03K19/0185
CPC分类号： H03K19/018514 , H03K5/1515 , H03K2005/00136 , H03M1/0863 , H03M1/742
摘要： A ratio asymmetric inverter has a signal input, signal output, first and second power inputs, pullup and pulldown transistors, and at least one delay element. The pullup transistor has a gate terminal, a source terminal coupled to the first power input, and a drain terminal coupled to the signal output. The pulldown transistor has a gate terminal, a drain terminal coupled to the signal output, and a source terminal coupled to the second power input. The signal input is respectively coupled to the gate terminals of the pullup transistor and the pulldown transistor via first and second signal paths. The at least one delay element is included in only one of the first and second signal paths, to impart a longer propagation delay to the one of the first and second signal paths.
摘要翻译：比例非对称逆变器具有信号输入，信号输出，第一和第二功率输入，上拉和下拉晶体管以及至少一个延迟元件。上拉晶体管具有栅极端子，耦合到第一电力输入端的源极端子和耦合到信号输出端的漏极端子。下拉晶体管具有栅极端子，耦合到信号输出的漏极端子和耦合到第二电力输入端的源极端子。信号输入分别经由第一和第二信号路径耦合到上拉晶体管和下拉晶体管的栅极端子。至少一个延迟元件仅包括在第一和第二信号路径中的一个中，以向第一和第二信号路径中的一个施加更长的传播延迟。

7. 发明授权

US06404243B1 System and method for controlling delay times in floating-body CMOSFET inverters 失效
标题翻译：用于控制浮体CMOSFET逆变器的延迟时间的系统和方法
公开(公告)号：US06404243B1
公开(公告)日：2002-06-11
申请号：US09759718
申请日：2001-01-12
申请人： Kenneth Koch, II , William Weiner
发明人： Kenneth Koch, II , William Weiner
IPC分类号： H03B2100
CPC分类号： H03K5/159 , H03K5/133 , H03K19/0013 , H03K19/01707 , H03K2005/00136
摘要： The present invention discloses a floating body architecture CMOSFET inverter with body biasing inverters added for controlling the delay time of the inverter. At least one body biasing inverter is connected between the main inverter's input and the body terminals of the FETs of the inverter. By supplying a representation of the input voltage to the body terminals of the p-channel and n-channel FETs, the preferred embodiment of the present invention is able to control the history dependent delay time associated with the variable source-to-body voltages in floating body CMOSFET inverters. The delay time is minimized by adding an odd number of body biasing inverter stages into the main inverter circuit. The delay time can also be maximized by adding an even number of body biasing inverter stages into the circuit.
摘要翻译：本发明公开了一种用于控制逆变器的延迟时间的体积偏置逆变器的浮体结构CMOSFET逆变器。在主逆变器的输入端和变频器的FET的主体端子之间连接有至少一个主体偏置逆变器。通过向p沟道和n沟道FET的体式端子提供输入电压的表示，本发明的优选实施例能够控制与可变源极对体电压相关联的与历史相关的延迟时间浮体CMOSFET逆变器。通过向主逆变器电路中添加奇数个体偏置反相器级来延迟时间被最小化。通过在电路中添加偶数个体偏置反相器级，延迟时间也可以最大化。

8. 发明申请

US20020057121A1 Trip-point adjustment and delay chain circuits 有权
公开(公告)号：US20020057121A1
公开(公告)日：2002-05-16
申请号：US09494619
申请日：2000-01-31
发明人： Andy L. Lee
IPC分类号： H03H011/26
CPC分类号： H03K19/0027 , H03K5/133 , H03K2005/00136
摘要： Circuit techniques provide different trip points for a rising-edge and for a falling-edge input to a logic gate. Adjustment of the gate trip point for a rising-edge input may be independently adjusted to that for the falling-edge input, and vice versa. Different circuit topologies are provided for delay chains on integrated circuits. Each implementation allows flexibility in delay elements through metal options to allow modifying delay chain delays with simple metal-only layout changes. Delay chains are used in integrated circuits to produce either a constant delay or to track another circuit delay.

9. 发明授权

US06362672B1 Apparatus and method for automatic matching of signaling rise time to fall time 失效
标题翻译：自动匹配信号上升时间与下降时间的装置和方法
公开(公告)号：US06362672B1
公开(公告)日：2002-03-26
申请号：US09778771
申请日：2001-02-08
申请人： Alan S. Geist
发明人： Alan S. Geist
IPC分类号： H03K512
CPC分类号： H03K5/13 , H03K5/082 , H03K19/00323 , H03K2005/00136
摘要： A method and apparatus for matching rise time and fall time in two differential signals. The apparatus includes a system that includes an scaled summer, a reference voltage generator, a comparator, and a storage device. The scaled summer receives two input signals and generates an instantaneous scaled sum of the two input signals. The reference voltage generator generating a reference voltage. The comparator compares the scaled summer output signal and the reference voltage and generates a comparison signal. The storage device stores the comparison signal. The stored comparison signal is usable to adjust one of the rise time and the fall time of both of the two input signals to match one of the fall time and the rise time of the two input signals.
摘要翻译：一种用于匹配两个差分信号中的上升时间和下降时间的方法和装置。该装置包括包括缩放的夏天，参考电压发生器，比较器和存储装置的系统。缩放的夏季接收两个输入信号，并产生两个输入信号的瞬时缩放和。参考电压发生器产生参考电压。比较器比较缩放的夏季输出信号和参考电压，并产生比较信号。存储装置存储比较信号。存储的比较信号可用于调整两个输入信号两者的上升时间和下降时间之一，以匹配两个输入信号的下降时间和上升时间之一。

10. 发明授权

US5338990A Regulated delay line 失效
标题翻译：调节延时线
公开(公告)号：US5338990A
公开(公告)日：1994-08-16
申请号：US019784
申请日：1993-02-19
申请人： Perry W. Lou
发明人： Perry W. Lou
IPC分类号： H03K5/00 , H03K5/13 , H03K5/159 , H03K3/01
CPC分类号： H03K5/131 , H03K2005/00097 , H03K2005/00136
摘要： Three delay lines may have common characteristics. The first delay line delays the rising edge of an input signal and a first inverter inverts this signal to provide a falling edge. A second inverter inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line in a second path with the second inverter. The signals from the two paths may be introduced to a comparator which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal. This voltage is introduced to the first and second delay lines to adjust their delay to minimize the time difference in the falling edges of the signals from these lines. This voltage is also introduced to the third delay line to adjust its delay in accordance with the adjustments in the delays in the first and second lines. In this way, the third delay line provides the same time for rising edges and falling edges in data signals introduced to the line.
摘要翻译：三条延迟线可能具有共同特征。第一延迟线延迟输入信号的上升沿，第一反相器反相该信号以提供下降沿。第二反相器反转输入信号的上升沿，产生下降沿，该下降沿与第二反相器以第二路径被引入第二延迟线。来自两个路径的信号可以被引入比较器，该比较器产生具有逻辑电平的控制信号，该逻辑电平取决于两个路径中的信号的下降沿的相对时间。例如，当下降沿首先在第一路径中发生时，控制信号可以具有第一逻辑电平，并且当下降沿首先在第二路径中发生时，控制信号可能具有第二逻辑电平。来自电荷泵的电压根据控制信号的逻辑电平进行调节。该电压被引入到第一和第二延迟线以调整它们的延迟以最小化来自这些线的信号的下降沿中的时间差。该电压也被引入第三延迟线，以根据第一和第二线中的延迟的调整来调整其延迟。以这种方式，第三延迟线为引入到线路的数据信号中的上升沿和下降沿提供相同的时间。

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