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31. 发明授权

US06812514B1 High density floating gate flash memory and fabrication processes therefor 有权
标题翻译：高密度浮栅闪存及其制造工艺
公开(公告)号：US06812514B1
公开(公告)日：2004-11-02
申请号：US10660420
申请日：2003-09-10
申请人： Nian Yang , Zhigang Wang , Hyeon-seag Kim
发明人： Nian Yang , Zhigang Wang , Hyeon-seag Kim
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate flash memory device including a substrate including a source region, a drain region and a channel region positioned therebetween; a stack gate including a floating gate electrode, at least one of sidewall/spacers, second sidewalls or a barrier layer, in which the floating gate is positioned above the channel region. The floating gate may be separated from the channel region by one or more of a reverse tunnel dielectric layer, the barrier layer and a pad dielectric layer. The floating gate may be a metal floating gate.
摘要翻译：一种浮栅闪存器件，包括：衬底，其包括源极区，漏极区和位于其间的沟道区; 包括浮置栅电极的堆叠栅极，侧壁/间隔物，第二侧壁或阻挡层中的至少一个，浮栅位于沟道区的上方。浮栅可以通过反向隧道介电层，阻挡层和焊盘介电层中的一个或多个与沟道区分离。浮动栅极可以是金属浮动栅极。

32. 发明授权

US06808945B1 Method and system for testing tunnel oxide on a memory-related structure 有权
标题翻译：用于在存储器相关结构上测试隧道氧化物的方法和系统
公开(公告)号：US06808945B1
公开(公告)日：2004-10-26
申请号：US10339536
申请日：2003-01-08
申请人： Zhigang Wang , Hsiao Han Thio , Nian Yang
发明人： Zhigang Wang , Hsiao Han Thio , Nian Yang
IPC分类号： G01R3126
CPC分类号： H01L22/34 , G11C16/04 , G11C29/006 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , G11C2029/5006 , H01L21/28282
摘要： A method for testing tunnel oxide on a memory-related structure. In one method embodiment, the present invention accesses a memory-related structure during a manufacturing process. Next, the present embodiment applies a constant voltage to a gate of the memory-related structure. The present embodiment then measures a first gate current for the memory-related structure when the constant voltage is initially applied, to obtain a first value. Next, the present embodiment measures a second gate current for the memory-related structure a period of time after the constant voltage is initially applied to obtain a second value. A calculation of ratio of the second value to the first value is then performed. The present embodiment then generates a graph of the first value and the ratio of the second value to the first value as a function of time, wherein a decrease in the graph signifies stress induced electron trapping behavior of the tunnel oxide.
摘要翻译：一种用于在存储器相关结构上测试隧道氧化物的方法。在一个方法实施例中，本发明在制造过程中访问存储器相关结构。接下来，本实施例对存储器相关结构的栅极施加恒定电压。然后，本实施例在最初施加恒定电压时测量用于存储器相关结构的第一栅极电流，以获得第一值。接下来，本实施例在初始施加恒定电压之后的一段时间内测量存储器相关结构的第二栅极电流，以获得第二值。然后执行第二值与第一值的比率的计算。本实施例然后产生第一值和第二值与第一值的比值作为时间的函数的曲线图，其中图形的减小表示隧道氧化物的应力诱导的电子捕获行为。

33. 发明授权

US06759295B1 METHOD OF DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING A GATE CURRENT MEASUREMENT TECHNIQUE FOR FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE AND DEVICE THEREBY FORMED 有权
标题翻译：使用栅极电流测量技术确定闪存隔离结构之间的活动区域宽度的方法，用于制造闪速存储器半导体器件及其形成的器件
公开(公告)号：US06759295B1
公开(公告)日：2004-07-06
申请号：US10224737
申请日：2002-08-20
申请人： Tien-Chun Yang , Nian Yang , Zhigang Wang
发明人： Tien-Chun Yang , Nian Yang , Zhigang Wang
IPC分类号： H01I21336
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method of determining the active region width (10) of an active region (4) by measuring the respective gate currents (Ig,100, Ig,100′, Ig,100″) of respective composite capacitance structures (100, 100′, 100″), respectively comprising at least one capacitor element (16, 17, 18; 16′, 17′, 18″; 16″, 17″, 18″) having respective predetermined widths (Wi) for fabricating a flash memory semiconductor device, and a device thereby fabricated. The present method also comprises plotting the respective gate currents (Ig,100, Ig,100 ′, Ig,100″) as a quasi-linear function (IW) of the respective predetermined widths (Wi), extrapolating a calibration term (WI=0) from the quasi-linear function (IW), and subtracting the calibration term (WIg=0) from the respective predetermined widths (Wi) to define and constrain the active region width (10) for facilitating device fabrication.
摘要翻译：通过测量各个复合电容结构（100,100'）的相应栅极电流（Ig，100，Ig，100'，Ig，100“）来确定有源区（4）的有源区宽度（10）的方法，，100“），分别包括至少一个具有相应预定宽度（Wi）的电容器元件（16,17,18; 16'，17”，18“，16”，17“，18”），制造闪速存储器半导体器件，以及由此制造的器件。本方法还包括将相应的栅极电流（Ig，100，Ig，100'，Ig，100“）绘制为各个预定宽度（Wi）的准线性函数（IW），外推校准项 = 0），并从相应的预定宽度（Wi）减去校准项（WIg = 0），以限定和约束有源区宽度（10）以便于器件制造。

34. 发明授权

US06756806B1 Method of determining location of gate oxide breakdown of MOSFET by measuring currents 有权
标题翻译：通过测量电流确定MOSFET栅极氧化物击穿位置的方法
公开(公告)号：US06756806B1
公开(公告)日：2004-06-29
申请号：US10113017
申请日：2002-03-28
申请人： Nian Yang , Zhigang Wang , Tien-Chun Yang
发明人： Nian Yang , Zhigang Wang , Tien-Chun Yang
IPC分类号： G01R3106
CPC分类号： G01R31/2621 , G01R31/2623 , G01R31/275
摘要： A method of determining the location of the breakdown in the gate oxide of a MOSFET is disclosed. Additionally, the method determines the location of the breakdown in a manner that is convenient to use and can be easily employed. The method will determine whether there is a breakdown in the gate oxide. If there is a breakdown, the method will enable determination of the location of the breakdown in the gate oxide.
摘要翻译：公开了一种确定MOSFET栅极氧化层中击穿位置的方法。此外，该方法以易于使用并且可以容易地使用的方式确定击穿的位置。该方法将确定栅极氧化物是否有故障。如果存在故障，则该方法将能够确定栅极氧化物中的击穿位置。

35. 发明授权

US06731130B1 Method of determining gate oxide thickness of an operational MOSFET 有权
标题翻译：确定工作MOSFET栅极氧化物厚度的方法
公开(公告)号：US06731130B1
公开(公告)日：2004-05-04
申请号：US10017832
申请日：2001-12-12
申请人： Nian Yang , Zhigang Wang , Tien-Chun Yang
发明人： Nian Yang , Zhigang Wang , Tien-Chun Yang
IPC分类号： G01R3126
CPC分类号： H01L22/20 , H01L22/12
摘要： A non-destructive and non-intrusive, user friendly, easy to setup and efficient system and method of determining the gate oxide thickness of an operational MOSFET used in real circuit applications is provided. Additionally, the present invention determines the gate oxide thickness when the operational MOSFET is operating in the inversion mode.
摘要翻译：提供了一种用于确定在实际电路应用中使用的工作MOSFET的栅极氧化物厚度的非破坏性和非侵入性，用户友好的易于设置和有效的系统和方法。此外，本发明在操作MOSFET以反转模式工作时确定栅极氧化物厚度。

36. 发明授权

US06689666B1 Replacing a first liner layer with a thicker oxide layer when forming a semiconductor device 有权
标题翻译：在形成半导体器件时，用较厚的氧化物层代替第一衬里层
公开(公告)号：US06689666B1
公开(公告)日：2004-02-10
申请号：US10126841
申请日：2002-04-19
申请人： Hsiao-Han Thio , Nian Yang , Zhigang Wang
发明人： Hsiao-Han Thio , Nian Yang , Zhigang Wang
IPC分类号： H01L21336
CPC分类号： H01L29/66553 , H01L21/28247 , H01L21/823468 , H01L21/823481 , H01L29/6656
摘要： A method (300) of fabricating a semiconductor device. An oxide layer (220) is produced on a sidewall (211) of a stacked gate (210) and over a shallow trench (212) adjacent to the stacked gate. The thickness of the oxide layer is sufficient to withstand a subsequent etch. A first layer (222) of material is deposited over the oxide layer. In a first etch, the first layer is reduced to a first thickness along the sidewall. Because the oxide layer has a depth sufficient to withstand the first etch, the oxide layer serves as a protective layer for the shallow trench during the first etch. Accordingly, a protective liner layer does not need to be deposited in addition to the oxide layer.
摘要翻译：一种制造半导体器件的方法（300）。在层叠栅极（210）的侧壁（211）上和与堆叠栅极相邻的浅沟槽（212）之上产生氧化物层（220）。氧化物层的厚度足以承受随后的蚀刻。材料的第一层（222）沉积在氧化物层上。在第一蚀刻中，第一层沿侧壁被还原成第一厚度。因为氧化物层具有足以承受第一蚀刻的深度，所以氧化物层在第一次蚀刻期间用作浅沟槽的保护层。因此，除了氧化物层之外，不需要沉积保护衬垫层。

37. 发明授权

US06660588B1 High density floating gate flash memory and fabrication processes therefor 有权
标题翻译：高密度浮栅闪存及其制作工艺
公开(公告)号：US06660588B1
公开(公告)日：2003-12-09
申请号：US10244229
申请日：2002-09-16
申请人： Nian Yang , Zhigang Wang , Hyeon-seag Kim
发明人： Nian Yang , Zhigang Wang , Hyeon-seag Kim
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A process for fabrication of a floating gate flash memory device, and the device made thereby, including providing a semiconductor substrate; forming a pad dielectric layer overlying the substrate; forming a hard mask layer overlying the pad dielectric layer; forming an initial trench through the hard mask layer, wherein the initial trench has an initial lateral extent Li defined by opposite hard mask sidewalls in the hard mask layer; reducing the initial lateral extent Li of the initial trench to define a reduced trench having a reduced lateral extent Lrx, wherein x is at least one; and filling the reduced trench with a floating gate material.
摘要翻译：一种用于制造浮动栅极闪存器件的方法及其制造的器件，包括提供半导体衬底; 形成覆盖所述基板的焊盘电介质层; 形成覆盖所述焊盘介电层的硬掩模层; 通过所述硬掩模层形成初始沟槽，其中所述初始沟槽具有由所述硬掩模层中的相对的硬掩模侧壁限定的初始横向延伸度; 减小初始沟槽的初始横向范围Li以限定具有减小的横向范围Lrx的减小的沟槽，其中x为至少一个; 并用浮栅材料填充还原的沟槽。

38. 发明授权

US06596586B1 Method of forming low resistance common source line for flash memory devices 失效
标题翻译：形成用于闪存器件的低电阻公共源线的方法
公开(公告)号：US06596586B1
公开(公告)日：2003-07-22
申请号：US10152747
申请日：2002-05-21
申请人： Nian Yang , Un Soon Kim , Zhigang Wang
发明人： Nian Yang , Un Soon Kim , Zhigang Wang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11517
摘要： A low resistance common source line (12) for high performance NOR-type flash memories cells in different bit-lines but on the same word-line is used to reduce the memory core cell size and to improve the circuit density as the device dimensions are scaled down. For advanced flash memory technology where shallow trench isolation (STI) (4) is used, the common source formation (12) is facilitated by a VCI implant (11) performed before STI field oxide fill (5). The process sequence is to first form the trenches (4) for the subsequent STI (4), then apply the VCI mask (10) and perform the VCI high energy ion implant (11) to form the “future” source line (12). Then field oxide fill (5) is deposited into the STI trench (4) to form the desired field isolation structures and the memory circuit is completed using conventional techniques.
摘要翻译：用于不同位线但在相同字线上的高性能NOR型闪速存储器单元的低电阻公共源线（12）用于减小存储器核心单元的尺寸并提高电路密度，因为器件尺寸缩小比例。对于使用浅沟槽隔离（STI）（4））的高级闪存技术，通过在STI场氧化物填充（5）之前执行的VCI注入（11）来促进公共源形成（12）。处理顺序是首先形成随后的STI（4）的沟槽（4），然后施加VCI掩模（10）并执行VCI高能离子注入（11）以形成“未来”源极线（12）。然后将场氧化物填充物（5）沉积到STI沟槽（4）中以形成所需的场隔离结构，并且使用常规技术完成存储器电路。

39. 发明授权

US06593590B1 Test structure apparatus for measuring standby current in flash memory devices 失效
标题翻译：用于测量闪存器件中待机电流的测试结构设备
公开(公告)号：US06593590B1
公开(公告)日：2003-07-15
申请号：US10112976
申请日：2002-03-28
申请人： Nian Yang , Zhigang Wang , Tien-Chun Yang
发明人： Nian Yang , Zhigang Wang , Tien-Chun Yang
IPC分类号： H01L2906
CPC分类号： H01L22/34 , G11C16/04 , G11C29/50 , G11C2029/5006 , H01L27/105
摘要： A flash memory microelectronic chip (1000) is formed with at least one integral test structure (100) for electrical measurement of transistor leakage current from the low voltage peripheral transistors. The invention is a very wide finger-type transistor (9, 10) with minimum channel length and a width of approximately 150,000 &mgr;m, equal to the estimated total width of the same type of periphery transistors in the chip circuit. One low voltage NMOS (9) and one low voltage PMOS finger-type transistor (10) allow monitoring of the standby current contribution from these two types of periphery transistors. Regular current or voltage tests can be applied to the test structure, thus providing information on the correlation of standby currents with single transistor off-state leakage currents.
摘要翻译：闪存微电子芯片（1000）形成有至少一个整体测试结构（100），用于电子测量来自低电压外围晶体管的晶体管漏电流。本发明是一种非常宽的手指式晶体管（9,10），其具有最小的通道长度和大约150,000μm的宽度，等于芯片电路中相同类型的外围晶体管的估计总宽度。一个低电压NMOS（9）和一个低电压PMOS指状晶体管（10）允许监测来自这两种类型的外围晶体管的待机电流贡献。可以对测试结构进行常规电流或电压测试，从而提供关于待机电流与单晶体管截止状态漏电流的相关性的信息。

40. 发明授权

US06486682B1 Determination of dielectric constants of thin dielectric materials in a MOS (metal oxide semiconductor) stack 失效
标题翻译：确定MOS（金属氧化物半导体）堆叠中的薄介电材料的介电常数
公开(公告)号：US06486682B1
公开(公告)日：2002-11-26
申请号：US09904736
申请日：2001-07-13
申请人： Zhigang Wang , Nian Yang , Tien-Chun Yang
发明人： Zhigang Wang , Nian Yang , Tien-Chun Yang
IPC分类号： H01L2358
CPC分类号： H01L22/34
摘要： First and second dielectric constants, e1 and e2 respectively, for first and second dielectric materials forming a MOS (metal oxide semiconductor) stack are determined. First and second test MOS stacks having first and second total effective oxide thickness, EOTA and EOTB, respectively, are formed. The first and second test MOS stacks include first and second interfacial structures comprised of the second dielectric material with first and second thickness, T2A and T1A, respectively. In addition, the first and second test MOS stacks include first and second high-K structures comprised of the first dielectric material with first and second thickness, T2B and T1B, respectively. The thickness parameters EOTA, T1A, T2A, EOTB, T1B, and T2B of the test MOS stacks are measured. The dielectric constants, e1 and e2, are then determined depending on relations between values of EOTA, T1A, and T2A, and between values of EOTB, T1B, and T2B.
摘要翻译：确定形成MOS（金属氧化物半导体）堆叠的第一和第二介电材料的第一和第二介电常数e1和e2。形成具有第一和第二总有效氧化物厚度的第一和第二测试MOS堆叠，分别为EOTA和EOTB。第一和第二测试MOS堆叠包括分别具有第一和第二厚度的第二介电材料的第一和第二界面结构，T2A和T1A。此外，第一和第二测试MOS堆叠包括分别由第一和第二厚度的第一介电材料构成的第一和第二高K结构，分别为T2B和T1B。测量MOS堆叠的厚度参数EOTA，T1A，T2A，EOTB，T1B和T2B。然后根据EOTA，T1A和T2A的值之间以及EOTB，T1B和T2B的值之间的关系确定介电常数e1和e2。

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