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31. 发明授权

US06646914B1 Flash memory array architecture having staggered metal lines 有权
标题翻译：具有交错金属线的闪存阵列架构
公开(公告)号：US06646914B1
公开(公告)日：2003-11-11
申请号：US10096313
申请日：2002-03-12
申请人： Sameer Haddad , Richard Fastow
发明人： Sameer Haddad , Richard Fastow
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C16/0416
摘要： A memory array includes a plurality of sets of transistors, each set including a pair of transistors in series. Each such pair of transistors is connected between a pair of adjacent bit lines. Each of the pair of transistors in each set is associated with a different one of an adjacent pair of word lines. The array is configured by providing substantially strait elongated source/drain regions in side-by-side, parallel relation. Each bit line has a zigzag configuration and connects to a pair of adjacent source/drain regions in alternating manner along the bit line length.
摘要翻译：存储器阵列包括多组晶体管，每组晶体管包括串联的一对晶体管。每对这样的晶体管连接在一对相邻的位线之间。每组中的每对晶体管与相邻的一对字线中的不同的一个相关联。该阵列通过以并排的平行关系提供基本上两条细长的源极/漏极区域来配置。每个位线具有之字形配置并且沿着位线长度交替地连接到一对相邻的源极/漏极区域。

32. 发明授权

US5999452A Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory 失效
标题翻译：双源多晶硅选择门结构和编程方法，利用单隧道氧化物进行NAND阵列闪存
公开(公告)号：US5999452A
公开(公告)日：1999-12-07
申请号：US63688
申请日：1998-04-21
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

33. 发明授权

US5912489A Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory 失效
标题翻译：双源端多晶硅选择门结构利用单隧道氧化物用于NAND阵列闪存
公开(公告)号：US5912489A
公开(公告)日：1999-06-15
申请号：US940674
申请日：1997-09-30
申请人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
发明人： Pau-Ling Chen , Mike Van Buskirk , Shane Charles Hollmer , Binh Quang Le , Shoichi Kawamura , Chung-You Hu , Yu Sun , Sameer Haddad , Chi Chang
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0483
摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.
摘要翻译：串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。串联选择晶体管连接到NAND串中的最后一个晶体管。源选择晶体管连接到阵列Vss电源。为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

34. 发明授权

US5856946A Memory cell programming with controlled current injection 失效
标题翻译：采用可控电流注入的存储单元编程
公开(公告)号：US5856946A
公开(公告)日：1999-01-05
申请号：US831571
申请日：1997-04-09
申请人： Vei-Han Chan , Sameer Haddad , Chi Chang
发明人： Vei-Han Chan , Sameer Haddad , Chi Chang
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/12
摘要： A memory with controlled gate current injection during memory cell programming wherein programming circuitry applies a time-varying voltage to a control gate of the memory cell during a programming cycle. The time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate during the programming cycle.
摘要翻译：在存储器单元编程期间具有受控栅极电流注入的存储器，其中编程电路在编程周期期间将时变电压施加到存储器单元的控制栅极。在编程周期期间，随时间变化的电压产生从通道区域到浮动栅极的电子流量的基本恒定的速率。

35. 发明授权

US07989328B2 Resistive memory array using P-I-N diode select device and methods of fabrication thereof 有权
标题翻译：使用P-I-N二极管选择装置的电阻式存储器阵列及其制造方法
公开(公告)号：US07989328B2
公开(公告)日：2011-08-02
申请号：US11641646
申请日：2006-12-19
申请人： Seungmoo Choi , Sameer Haddad
发明人： Seungmoo Choi , Sameer Haddad
IPC分类号： H01L21/38
CPC分类号： H01L27/2409 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C17/06 , H01L21/2256 , H01L27/24 , H01L27/2463 , H01L29/6609 , H01L29/868 , H01L45/1608
摘要： An electronic structure includes a resistive memory device, and a P-I-N diode in operative association with the resistive memory device. A plurality of such electronic structures are used in a resistive memory array, with the P-I-N diodes functioning as select devices in the array. Methods are provided for fabricating such resistive memory device-P-I-N diode structures.
摘要翻译：电子结构包括电阻性存储器件和与电阻式存储器件可操作地相关联的P-I-N二极管。在电阻式存储器阵列中使用多个这样的电子结构，其中P-I-N二极管用作阵列中的选择器件。提供了制造这种电阻式存储器件-P-I-N二极管结构的方法。

36. 发明授权

US07916523B2 Method of erasing a resistive memory device 有权
标题翻译：擦除电阻式存储器件的方法
公开(公告)号：US07916523B2
公开(公告)日：2011-03-29
申请号：US11633941
申请日：2006-12-05
申请人： An Chen , Sameer Haddad , Yi-Ching Jean Wu , Swaroop Kaza
发明人： An Chen , Sameer Haddad , Yi-Ching Jean Wu , Swaroop Kaza
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0097 , G11C2013/0071 , G11C2213/32 , G11C2213/72 , G11C2213/79
摘要： In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.
摘要翻译：在擦除电阻式存储器件的第一种方法中，将电位施加到与电阻性存储器件串联的晶体管的栅极，并且通过电阻存储器件提供连续增加的电流，通过提供连续增加的电势跨越电阻式存储器件。在擦除电阻性存储器件的第二种方法中，电阻被施加在电阻存储器件两端，并且通过电阻存储器件提供连续增加的电流，通过向晶体管的栅极串联提供连续增加的电势，电阻式存储器件。

37. 发明申请

US20080112206A1 Method of selecting operating characteristics of a resistive memory device 有权
标题翻译：选择电阻式存储器件的工作特性的方法
公开(公告)号：US20080112206A1
公开(公告)日：2008-05-15
申请号：US11590378
申请日：2006-10-31
申请人： Tzu-Ning Fang , Swaroop Kaza , An Chen , Sameer Haddad
发明人： Tzu-Ning Fang , Swaroop Kaza , An Chen , Sameer Haddad
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/52 , H01L27/2409 , H01L27/2436 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.
摘要翻译：在提供电阻存储器件的工作特性的方法中，选择其电极的材料，从而提供器件的选定工作特性。电极的材料可以与电阻式存储器件的绝缘层的材料反应以形成反应层，所选择的操作特性取决于反应层的存在。

38. 发明申请

US20060256608A1 Resistive memory device with improved data retention and reduced power 审中-公开
标题翻译：电阻式存储器件，具有改进的数据保持和降低功耗
公开(公告)号：US20060256608A1
公开(公告)日：2006-11-16
申请号：US11126800
申请日：2005-05-11
申请人： An Chen , Sameer Haddad , Tzu-Ning Fang
发明人： An Chen , Sameer Haddad , Tzu-Ning Fang
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C13/0069 , G11C2013/009 , G11C2213/12 , G11C2213/15 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Provided herein is method of programming a resistive memory device, the resistive memory device including a first electrode, a second electrode, a passive layer between the first and second electrode, and an active layer between the first and second electrodes. In the programming method, an electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the active layer to the passive layer so that electronic charge carriers enter the active layer and are held by traps therein. In erasing the memory device, an electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the passive layer to the active layer so that electronic charge carriers are moved from the active layer.
摘要翻译：本文提供了对电阻式存储器件进行编程的方法，该电阻式存储器件包括第一电极，第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层。在编程方法中，在从有源层到无源层的方向上，跨越第一和第二电极施加电位从较高电位到较低的电位，使得电子载流子进入有源层并由其中的陷阱保持。在擦除存储器件时，在从无源层到有源层的方向上，跨越第一和第二电极的电势从较高电位施加到较低的电位，使得电子载流子从有源层移动。

39. 发明授权

US06953752B1 Reduced silicon gouging and common source line resistance in semiconductor devices 失效
标题翻译：在半导体器件中减少硅沟槽和普通源极线电阻
公开(公告)号：US06953752B1
公开(公告)日：2005-10-11
申请号：US10358756
申请日：2003-02-05
申请人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang , Richard Fastow
发明人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang , Richard Fastow
IPC分类号： H01L21/311 , H01L21/8247
CPC分类号： H01L27/11521
摘要： In the present method of undertaking a self aligned source etch of a semiconductor structure, a substrate has oxide thereon. First and second adjacent stacked gate structures are provided on the substrate. Oxide spacers are provided on the respective first and second adjacent sides of the first and second gate stacked structures, and polysilicon spacers are provided on the respective oxide spacers. A self aligned source etch is undertaken using the gate structures, oxide spacers, and polysilicon spacers as a mask. The polysilicon spacers are then removed, and metal, for example cobalt, is provided on the substrate, using the oxide spacers as a mask. A silicidation step is undertaken to form metal silicide common source line on the substrate.
摘要翻译：在进行半导体结构的自对准源蚀刻的本方法中，衬底在其上具有氧化物。第一和第二相邻的堆叠栅极结构设置在基板上。在第一和第二栅极堆叠结构的相应的第一和第二相邻侧上设置氧化物间隔物，并且在各个氧化物间隔物上设置多晶硅间隔物。使用栅极结构，氧化物间隔物和多晶硅间隔物作为掩模进行自对准源蚀刻。然后去除多晶硅间隔物，并且使用氧化物间隔物作为掩模在衬底上提供金属（例如钴）。进行硅化步骤以在衬底上形成金属硅化物共同源极线。

40. 发明申请

US20050077567A1 Memory cell array with staggered local inter-connect structure 失效
标题翻译：具有交错局部互连结构的存储单元阵列
公开(公告)号：US20050077567A1
公开(公告)日：2005-04-14
申请号：US10685044
申请日：2003-10-14
申请人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.
摘要翻译：存储单元阵列包括在半导体衬底上制造的存储器单元的二维阵列。存储单元布置成多行和多列。每列存储单元包括多个交替沟道区和源极/漏极区。导电互连位于每个源极/漏极区域上方并且仅耦合到另一个源极/漏极区域。另一个源/漏区位于与该列相邻的第二列中。导电互连被定位成使得每隔一个导电布线连接到列的右侧的相邻列，并且每隔一个导电布线连接到列的左侧的相邻列。多个源极/漏极控制线在相邻列的存储器单元之间延伸，并且电耦合到在相邻列之间耦合的每个导电互连。

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