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31. 发明授权

US06288585B1 Semiconductor device using external power voltage for timing sensitive signals 有权
标题翻译：半导体器件使用外部电源电压进行时序敏感信号
公开(公告)号：US06288585B1
公开(公告)日：2001-09-11
申请号：US09535745
申请日：2000-03-27
申请人： Yoshihide Bando , Nobutaka Taniguchi , Hiroyoshi Tomita , Kota Hara , Naoharu Shinozaki
发明人： Yoshihide Bando , Nobutaka Taniguchi , Hiroyoshi Tomita , Kota Hara , Naoharu Shinozaki
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C7/222 , H03L7/0812
摘要： A semiconductor device receiving a stable external power voltage includes a reduced-voltage-generation circuit which generates an internally reduced power voltage, an input circuit which operates based on the internally reduced power voltage, causing the internally reduced power voltage to fluctuate, a clock-control circuit which generates an internal clock signal, an output circuit which outputs a data signal to an exterior of the device at output timings responsive to the internal clock signal, a clock-delivery circuit which conveys the internal clock signal from the clock-control circuit to the output circuit, and operates based on the external power voltage such as to make the output timings substantially unaffected by fluctuation of the internally reduced power voltage.
摘要翻译：接收稳定的外部电源电压的半导体器件包括产生内部降低的电源电压的降压产生电路，基于内部降低的电源电压进行操作的输入电路，使内部降低的电源电压波动，控制电路，其产生内部时钟信号;输出电路，其响应于内部时钟信号以输出定时将数据信号输出到设备的外部;时钟传送电路，其传送来自时钟控制电路的内部时钟信号到输出电路，并且基于外部电源电压进行操作，以使得输出定时基本上不受内部降低的功率电压的波动的影响。

32. 发明授权

US06252804B1 Semiconductor integrated circuit, and method of controlling same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US06252804B1
公开(公告)日：2001-06-26
申请号：US09629619
申请日：2000-07-31
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： G11C1140
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1072 , G11C7/1078
摘要： A semiconductor integrated circuit comprising memory cells and a holding unit. The holding unit holds write data to the memory cell and mask information for masking a predetermined bit or bits of the write data, both supplied corresponding to a write command, as held write data and held mask information. On receiving a next write command, the semiconductor integrated circuit masks held write data in accordance with held mask information and writes the resultant to the memory cell. The holding unit holds next write data and next mask information supplied corresponding to this write command as held write data and held mask information. That is, the held write data and the held mask information are rewritten. Thereby, the semiconductor integrated circuit which writes write data previously accepted upon the reception of a next write command can mask the write data.
摘要翻译：一种包括存储单元和保持单元的半导体集成电路。保持单元将写入数据保存到存储单元，并且掩蔽信息，用于屏蔽对应于写入命令的写入数据的预定位或位，作为保持写入数据和保持的掩码信息。在接收到下一个写入命令时，半导体集成电路根据所保持的掩码信息掩蔽保持写入数据，并将结果写入存储单元。保持单元保持与该写入命令相对应的下一个写入数据和下一个掩模信息作为保持的写入数据和保持的掩码信息。也就是说，保持的写入数据和保持的掩码信息被重写。由此，在接收下一个写入命令时写入预先接受的写入数据的半导体集成电路可以掩蔽写入数据。

33. 发明授权

US06064625A Semiconductor memory device having a short write time 失效
标题翻译：具有短写入时间的半导体存储器件
公开(公告)号：US06064625A
公开(公告)日：2000-05-16
申请号：US1460
申请日：1997-12-31
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/408 , G11C8/00
CPC分类号： G11C29/84 , G11C7/1039 , G11C7/22 , G11C2207/229
摘要： The present invention internally latches a write data signal applied in synchronous with an external data strobe signal in response to an internal data strobe signal which is generated in response to this external data strobe signal, and furthermore, supplies the write data signal to a memory cell array from a write circuit such as a write amplifier in response to a write signal generated from this external data strobe signal. Meanwhile, an address signal is introduced internally in accordance with an external clock. Therefore, since the driving of the data bus connected to a memory cell array from a write amplifier, which constitutes a write operation internal to memory, commences in accordance with an external data strobe signal, a write operation can be ended in the shortest possible time from write data signal input. The above-described invention is especially effective when memory comprises a 2-bit pre-fetch. That is, a 2-bit write data signal is supplied time-sequentially in synchronous with an external data strobe signal. Since an internal write operation can commence after receiving for the input of that second write data signal, it enables the shortest write operation.
摘要翻译：本发明响应于响应于该外部数据选通信号而产生的内部数据选通信号，内部锁存与外部数据选通信号同步施加的写入数据信号，此外，将写入数据信号提供给存储单元响应于从该外部数据选通信号产生的写入信号，写入诸如写放大器的写入电路的阵列。同时，根据外部时钟在内部引入地址信号。因此，由于构成存储器内部的写操作的写放大器连接到存储单元阵列的数据总线的驱动根据外部数据选通信号开始，所以可以在最短的时间内结束写入操作从写数据信号输入。当存储器包括2位预取时，上述发明特别有效。也就是说，与外部数据选通信号同步地按时间顺序地提供2位写入数据信号。由于在接收到该第二写入数据信号的输入之后可以开始内部写入操作，所以能够进行最短的写入操作。

34. 发明授权

US5751652A Semiconductor apparatus having a voltage unit and a backup unit for providing a reduced power consumption 失效
标题翻译：具有电压单元的半导体装置和用于提供降低的功耗的备用单元
公开(公告)号：US5751652A
公开(公告)日：1998-05-12
申请号：US867044
申请日：1997-06-02
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： G11C11/413 , G05F1/46 , G05F3/24 , G11C5/14 , G11C11/407 , G11C11/409 , G11C13/00
CPC分类号： G11C5/143 , G11C5/147 , G05F1/465
摘要： A semiconductor apparatus includes a voltage unit which supplies a down voltage produced at a node, the voltage unit having a plurality of resistors connected in series between a power supply line and a grounding line, the node being a connection point between the plurality of resistors. A backup unit pulls up the node of the voltage unit when a voltage at the node is below a lower limit of the down voltage, so that the voltage at the node increases to the lower limit, and pulls down the node of the voltage unit when the voltage at the node is above an upper limit of the down voltage, so that the voltage at the node decreases to the upper limit. A control unit sets the backup unit in one of an active state and an inactive state in response to a control signal.
摘要翻译：半导体装置包括提供在节点处产生的降压的电压单元，所述电压单元具有串联连接在电源线和接地线之间的多个电阻器，所述节点是所述多个电阻器之间的连接点。当节点电压低于下降电压的下限时，备用单元拉电压单元的节点，使得节点处的电压上升到下限，并将电压单元的节点拉低节点处的电压高于降压的上限，使得节点处的电压下降到上限。控制单元响应于控制信号将备份单元设置为活动状态和非活动状态之一。

35. 发明授权

US5592433A Semiconductor memory device having a capability for controlled activation of sense amplifiers 失效
标题翻译：具有用于感测放大器的受控激活能力的半导体存储器件
公开(公告)号：US5592433A
公开(公告)日：1997-01-07
申请号：US643834
申请日：1996-05-07
申请人： Hiroyoshi Tomita , Makoto Yanagisawa , Yukinori Kodama
发明人： Hiroyoshi Tomita , Makoto Yanagisawa , Yukinori Kodama
IPC分类号： G11C7/06 , G11C13/00
CPC分类号： G11C7/065
摘要： A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same. The first and second conductor strips have distal end parts having a reduced width and a mutually complementary shape, such that the first and second conductor strips are disposed to form a straight strip having a substantially constant width throughout the memory cell array.
摘要翻译：一种半导体存储器件包括其中提供多个读出放大器的存储单元阵列，多个分段驱动线，每个驱动线连接到用于驱动读出放大器的一组读出放大器，每个分段驱动线由第一和第二形成一对的驱动线段和用于向分段驱动线提供电力的多个中继线。每个中继线包括从存储单元阵列的第一侧向第二侧延伸的第一导体条，用于在与第一驱动线段交叉时与多个第一驱动线段连接，第二导体条从第二侧延伸所述存储单元阵列朝向所述第一侧，用于在与所述第二驱动线段交叉时连接到所述第二驱动线段。第一和第二导体条具有具有减小的宽度和相互互补形状的远端部分，使得第一和第二导体条被设置成形成整个存储单元阵列具有基本恒定的宽度的直条。

36. 发明授权

US08351247B2 Semiconductor device including memory cell having capacitor 有权
标题翻译：包括具有电容器的存储单元的半导体器件
公开(公告)号：US08351247B2
公开(公告)日：2013-01-08
申请号：US12707044
申请日：2010-02-17
申请人： Hiroyuki Ogawa , Hiroyoshi Tomita , Masato Takita
发明人： Hiroyuki Ogawa , Hiroyoshi Tomita , Masato Takita
IPC分类号： G11C11/24
CPC分类号： H01L27/0207 , G11C5/063 , G11C7/02 , G11C7/18 , G11C11/4097 , H01L27/1085 , H01L27/10885 , H01L27/10897
摘要： A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.
摘要翻译：半导体器件包括半导体衬底; 存储单元阵列，包括形成在所述半导体衬底上并在所述半导体衬底的表面上沿第一方向和第二方向布置成矩阵的多个存储单元; 多个读出放大器，形成在半导体衬底上并包括第一读出放大器和第二读出放大器; 以及沿着存储单元阵列上方的第一方向延伸并沿第二方向并排布置的多个位线，其中多个位线包括形成在第一布线层中的第一位线对和第二位线形成在位于第一布线层上方的第二布线层中。

37. 发明授权

US08350310B2 Semiconductor device including memory cell having capacitor 有权
公开(公告)号：US08350310B2
公开(公告)日：2013-01-08
申请号：US13473242
申请日：2012-05-16
申请人： Hiroyuki Ogawa , Hiroyoshi Tomita , Masato Takita
发明人： Hiroyuki Ogawa , Hiroyoshi Tomita , Masato Takita
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , G11C5/063 , G11C7/02 , G11C7/18 , G11C11/4097 , H01L27/1085 , H01L27/10885 , H01L27/10897
摘要： A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.

38. 发明授权

US07719915B2 Semiconductor memory device including a terminal for receiving address signal and data signal 有权
标题翻译：半导体存储器件包括用于接收地址信号和数据信号的端子
公开(公告)号：US07719915B2
公开(公告)日：2010-05-18
申请号：US11653338
申请日：2007-01-16
申请人： Hiroyoshi Tomita , Shusaku Yamaguchi
发明人： Hiroyoshi Tomita , Shusaku Yamaguchi
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1045 , G11C11/40603 , G11C11/40615 , G11C11/4076
摘要： A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of read or write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.
摘要翻译：多功能终端接收地址信号和数据信号。地址有效终端接收地址有效信号，指示提供给多功能终端的信号是地址信号。仲裁者确定哪个外部访问请求和内部刷新请求被赋予优先级。响应于芯片使能信号和地址有效信号都达到有效电平（外部访问请求）的事实，仲裁器禁止接收内部新的请求。响应于读或写操作的完成，仲裁器使得能够接收内部刷新请求。结果，在包括接收地址信号和数据信号的多用途终端的半导体存储器件中，防止读取操作和写入操作之间的争用以及响应于内部刷新请求的刷新操作，这防止了故障。

39. 发明申请

US20080043510A1 Semiconductor memory device containing antifuse write voltage generation circuit 失效
标题翻译：含有反熔丝写电压生成电路的半导体存储器件
公开(公告)号：US20080043510A1
公开(公告)日：2008-02-21
申请号：US11889672
申请日：2007-08-15
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C5/145 , G11C5/147 , G11C11/406 , G11C11/40615 , G11C11/4074 , G11C17/165 , G11C17/18
摘要： A semiconductor memory device that enables the reduction of the circuit scale of the antifuse write voltage generation circuit. The semiconductor memory device has a first internal power supply generation circuit that boosts an external power supply voltage to generate a first internal power supply, a memory core to which the first internal power supply is supplied, an antifuse memory for writing predetermined information, and also a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage.
摘要翻译：一种半导体存储器件，其能够减少反熔丝写入电压产生电路的电路规模。半导体存储器件具有第一内部电源产生电路，其升高外部电源电压以产生第一内部电源，提供第一内部电源的存储器芯，用于写入预定信息的反熔丝存储器，以及写入电压产生电路，其升高第一内部电源以产生反熔丝写入电压。

40. 发明授权

US07319349B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07319349B2
公开(公告)日：2008-01-15
申请号：US11043333
申请日：2005-01-27
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： H03L7/00
CPC分类号： H03K5/133 , G06F1/12 , H03K2005/00058 , H03K2005/00071 , H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A phase adjustment unit adjusts the phases of a plurality of external clocks successively shifted in phase, thereby generating a plurality of internal clocks having an equal phase difference between every adjacent transition edges thereof. The internal clocks are synthesized to generate a composite clock having equal pulse intervals. Thus, even when the semiconductor integrated circuit is supplied with external clocks of lower frequencies, it is possible to operate the semiconductor integrated circuit at high speed. For example, the internal circuit can be operated and tested at high speed by using a low-cost LSI tester having a low clock frequency. This can reduce the testing cost of the semiconductor integrated circuit, allowing a reduction in chip cost.
摘要翻译：相位调整单元调整相位相移的多个外部时钟的相位，从而生成在其每个相邻过渡边缘之间具有相等相位差的多个内部时钟。内部时钟被合成以产生具有相等脉冲间隔的复合时钟。因此，即使在半导体集成电路被提供有较低频率的外部时钟的情况下，也可以高速地操作半导体集成电路。例如，通过使用具有低时钟频率的低成本LSI测试仪，可以高速地操作和测试内部电路。这可以降低半导体集成电路的测试成本，从而降低芯片成本。

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