专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US06944069B2 Semiconductor memory device having column select line driving scheme for reducing skew between column select lines and column select line driving method thereof 失效
标题翻译：具有用于减少列选择线之间的偏斜的列选择线驱动方案的半导体存储器件及其列选择线驱动方法
公开(公告)号：US06944069B2
公开(公告)日：2005-09-13
申请号：US10803845
申请日：2004-03-18
申请人： Byung-chul Kim , Seung-bum Ko
发明人： Byung-chul Kim , Seung-bum Ko
IPC分类号： G11C11/4094 , G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1048 , G11C11/4096 , G11C2207/002
摘要： Provided are a semiconductor memory device with a column select line (CSL) driving scheme capable of reducing skew between column select lines, and a CSL driving method. The semiconductor memory device includes a plurality of CSL enable controllers and a plurality of CSL disable controllers that are installed around corresponding CSL drivers, thereby making loads on input terminals of the CSL drivers almost the same and reducing enable and disable skew between the CSLs. The semiconductor memory device includes a plurality of enable master signal delayers that delay a signal output from a CSL enable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL enable controllers, and a plurality of disable master signal delayers that delay a signal output from a CSL disable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL disable controllers. It is possible to compensate for signal delay caused by different loads on signal transmission lines and further reduce enable and disable skew between the CSLs.
摘要翻译：提供了具有能够减少列选择线之间的偏斜的列选择线（CSL）驱动方案的半导体存储器件以及CSL驱动方法。半导体存储器件包括多个CSL使能控制器和多个安装在相应的CSL驱动器周围的CSL禁用控制器，从而使得CSL驱动器的输入端子上的负载几乎相同，并且减少了使能和禁止CSL之间的偏移。半导体存储器件包括多个使能主信号延迟器，其延迟从CSL使能主信号发生器输出的信号不同的时间，以产生不同的延迟信号并将延迟信号发送到多个CSL使能控制器，并且多个禁止主信号延迟器，其延迟来自CSL禁用主信号发生器的信号的不同时间，以产生不同的延迟信号并将延迟信号发送到多个CSL禁用控制器。可以补偿由信号传输线路上的不同负载引起的信号延迟，并进一步减少CSL之间的使能和禁止偏移。

32. 发明授权

US6123805A Discharge electrode and process chamber of dry etching facility for manufacturing semiconductor devices 有权
标题翻译：用于制造半导体器件的干蚀刻设备的放电电极和处理室
公开(公告)号：US6123805A
公开(公告)日：2000-09-26
申请号：US401960
申请日：1999-09-22
申请人： Tae-hoon Kim , Byung-chul Kim , Dong-hwan Ko
发明人： Tae-hoon Kim , Byung-chul Kim , Dong-hwan Ko
IPC分类号： H01L21/302 , H01J37/32 , H01L21/3065 , C23C16/00 , H05H1/00
CPC分类号： H01J37/32834
摘要： A process chamber of a dry etching facility for manufacturing semiconductor devices uniformly forms the ion density of plasma over a wafer, and reduces the volume of the process chamber by installing a plurality of discharge openings in an electrode housing which supports the electrode plate of a lower electrode. The lower electrode is a discharge electrode which is constructed such that a plurality of discharge openings are symmetrically provided in the side wall of the electrode housing supporting the electrode plate on which a wafer is mounted, and the discharge openings form a discharge passage which is connected to a discharge pipe at a pipe connection opening.
摘要翻译：用于制造半导体器件的干蚀刻设备的处理室在晶片上均匀地形成等离子体的离子密度，并且通过在电极壳体中安装多个排出孔来减小处理室的体积，所述电极壳体支撑下部电极板电极。下部电极是放电电极，其被构造成使得多个排出口对称地设置在支撑安装有晶片的电极板的电极壳体的侧壁中，并且排出开口形成连接的排出通道到管道连接开口处的排放管。

33. 发明授权

US6064601A Integrated circuit memory devices and controlling methods that simultaneously activate multiple column select lines during a write cycle of a parallel bit test mode 失效
标题翻译：在并行位测试模式的写周期期间同时激活多列选择线的集成电路存储器件和控制方法
公开(公告)号：US6064601A
公开(公告)日：2000-05-16
申请号：US104475
申请日：1998-06-25
申请人： Jei-hwan Yoo , Byung-chul Kim
发明人： Jei-hwan Yoo , Byung-chul Kim
IPC分类号： G01R31/28 , G11C29/00 , G11C29/32 , G11C29/34 , G11C16/04
CPC分类号： G11C29/32
摘要： Integrated circuit memory devices can reduce write time during a write cycle of a parallel bit test mode. The memory devices include a simultaneous column select line activation circuit that simultaneously activates at least two of the plurality of column select lines during a write cycle of a parallel bit test mode. Therefore, during the write cycle, at least two bit lines are simultaneously connected to one input and output line since at least two column select lines are simultaneously activated by the simultaneous column select line activation circuit. Accordingly, data is simultaneously written to the memory cells connected to at least two bit lines through the input and output line.
摘要翻译：集成电路存储器件可以在并行位测试模式的写周期期间减少写入时间。存储器件包括同时列选择线激活电路，其在并行位测试模式的写周期期间同时激活多个列选择线中的至少两个。因此，在写入周期期间，至少两条位线同时连接到一条输入和输出线，因为至少两条列选择线同时被同时列选择线激活电路激活。因此，通过输入和输出线将数据同时写入连接到至少两个位线的存储单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式