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1. 发明授权

US06937087B2 Temperature sensor and method for detecting trip temperature of a temperature sensor 有权
公开(公告)号：US06937087B2
公开(公告)日：2005-08-30
申请号：US10928498
申请日：2004-08-30
申请人： Jae-Yoon Sim , Jei-Hwan Yoo
发明人： Jae-Yoon Sim , Jei-Hwan Yoo
IPC分类号： G01K7/22 , G01K3/00 , G01K7/24 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/12 , H03K17/94 , H01L35/00
CPC分类号： G01K7/015 , G01K3/005
摘要： A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.

2. 发明申请

US20050073033A1 Semiconductor memory device 有权
公开(公告)号：US20050073033A1
公开(公告)日：2005-04-07
申请号：US10372336
申请日：2003-02-25
申请人： Jei-Hwan Yoo , Byung-Chul Kim , Won-Il Bae
发明人： Jei-Hwan Yoo , Byung-Chul Kim , Won-Il Bae
IPC分类号： G11C5/02 , G11C16/12 , H01L23/02 , H01L23/34
CPC分类号： G11C16/12
摘要： A semiconductor device package includes a plurality of semiconductor memory devices whose address input terminals are commonly connected to the external address input pins of the package, and an internal address generating device for using an address signal applied through at least one of the address input pins to select one of the memory devices to perform a read/write data operation. Only the selected memory device is enabled to perform the read/write operation on a memory cell corresponding to the received address signal. The external pin configuration of the semiconductor device package is compatible with a conventional memory board layout.

3. 发明申请

US20050030086A1 Negative voltage generator for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的负电压发生器
公开(公告)号：US20050030086A1
公开(公告)日：2005-02-10
申请号：US10940804
申请日：2004-08-26
申请人： Jae-Yoon Sim , Jei-Hwan Yoo
发明人： Jae-Yoon Sim , Jei-Hwan Yoo
IPC分类号： G11C5/14 , G11C16/30 , H02M3/07 , G11C8/00
CPC分类号： H02M3/07 , G11C5/147 , G11C16/30 , H02M2003/071
摘要： A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.
摘要翻译：响应于字线预充电信号控制负电压发生器。负偏置字线方案中的电压波动通过使用提升电路来在预充电操作期间提供预定量的负电荷来关闭字线来减小。负电压发生器包括第一和第二负电荷泵。响应于字线预充电信号激活第二电荷泵。负电压调节器可用于调节负电压信号。电平移位器使用两个分压器和差分放大器来减少响应时间，输出纹波和对过程和温度变化的敏感性。负电压调节器抵消来自电荷泵的纹波，以提供稳定的负偏置电压并减少预充电字线所需的电荷量。

4. 发明申请

US20050024097A1 Temperature sensor and method for detecting trip temperature of a temperature sensor 有权
标题翻译：用于检测温度传感器跳闸温度的温度传感器和方法
公开(公告)号：US20050024097A1
公开(公告)日：2005-02-03
申请号：US10928498
申请日：2004-08-30
申请人： Jae-Yoon Sim , Jei-Hwan Yoo
发明人： Jae-Yoon Sim , Jei-Hwan Yoo
IPC分类号： G01K7/22 , G01K3/00 , G01K7/24 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/12 , H03K17/94 , H03K5/153
CPC分类号： G01K7/015 , G01K3/005
摘要： A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.
摘要翻译：温度传感器的比较器电路包括输出节点和可变电流节点。当可变电流节点处的电流小于阈值电流时，输出节点是给定温度下的第一电压，以及当可变电流节点处的电流大于阈值电流时在给定温度下的不同的第二电压。可变电阻电路包括串联连接在比较器的可变电流节点和电源电压之间的至少n个不同电阻值的电阻器，其中n是4或更大的整数。提供开关电路以在测试序列期间选择性地旁路n个电阻器中的各个电阻器，以确定传感器的跳闸温度。

5. 发明授权

US06510096B2 Power down voltage control method and apparatus 有权
公开(公告)号：US06510096B2
公开(公告)日：2003-01-21
申请号：US09981945
申请日：2001-10-17
申请人： Jong-hyun Choi , Jei-hwan Yoo , Jong-eon Lee , Hyun-soon Jang
发明人： Jong-hyun Choi , Jei-hwan Yoo , Jong-eon Lee , Hyun-soon Jang
IPC分类号： G11C802
CPC分类号： G11C5/143 , G11C7/22
摘要： A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

6. 发明授权

US06490222B2 Decoding circuit for controlling activation of wordlines in a semiconductor memory device 失效
标题翻译：用于控制半导体存储器件中的字线激活的解码电路
公开(公告)号：US06490222B2
公开(公告)日：2002-12-03
申请号：US09875371
申请日：2001-06-05
申请人： Jong-Hyun Choi , Sang-Seok Kang , Jei-Hwan Yoo , Jae-Hoon Joo
发明人： Jong-Hyun Choi , Sang-Seok Kang , Jei-Hwan Yoo , Jae-Hoon Joo
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/14 , G11C29/34
摘要： A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.
摘要翻译：本发明的半导体存储器件包括：主解码器，用于响应于第一解码信号，第一预充电信号和第二预充电信号产生字线使能信号; 响应于字线使能信号和第二解码信号的字线驱动信号的字线驱动器; 以及用于响应于命令信号产生第二预充电信号的电路。响应于第一解码信号和第二预充电信号，字线驱动信号被顺序地去激活，以便减少地面噪声。

7. 发明授权

US06400620B1 Semiconductor memory device with burn-in test function 有权
标题翻译：具有老化测试功能的半导体存储器件
公开(公告)号：US06400620B1
公开(公告)日：2002-06-04
申请号：US09900728
申请日：2001-07-06
申请人： Jei-Hwan Yoo
发明人： Jei-Hwan Yoo
IPC分类号： G11C2900
CPC分类号： G11C29/787 , G11C29/26 , G11C29/44 , G11C29/50
摘要： Disclosed is a semiconductor memory device having a master fuse circuit, and an address storage and decoding circuit. The address storage and decoding circuit stores address information to assign a defective main cell of main cells, and receives current address information in response to switch control signals. During a burn-in test mode for the main cells, the master fuse circuit generates the switch control signals in response to a bum-in test signal indicating the bum-in test, for shutting the address information off not to be provided to the address storage and decoding circuit, regardless of a connected state of the master fuse.
摘要翻译：公开了具有主熔丝电路和地址存储和解码电路的半导体存储器件。地址存储和解码电路存储用于分配主单元的缺陷主单元的地址信息，并响应于开关控制信号接收当前地址信息。在主单元的老化测试模式期间，主熔丝电路响应于指示焊接测试的焊接测试信号产生开关控制信号，用于关闭不提供给地址的地址信息存储和解码电路，不管主保险丝的连接状态如何。

8. 发明授权

US06252263B1 Layout structure for dynamic random access memory 失效
标题翻译：动态随机存取存储器的布局结构
公开(公告)号：US06252263B1
公开(公告)日：2001-06-26
申请号：US09228039
申请日：1998-12-24
申请人： Jei-Hwan Yoo
发明人： Jei-Hwan Yoo
IPC分类号： H01L2710
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/4097 , H01L27/10852 , H01L27/10897
摘要： A layout structure of a semiconductor memory device having a memory cell array region, a word line drive region proximate the memory cell array, a bit line equalization region spaced apart from the memory cell array region, an impurity region formed between the memory cell array region and the bit line equalization region electrically coupled to the bit line equalization region, and a metal line extending over the impurity region supplying a bit line equalization voltage to the impurity region, wherein a contact connecting the metal line and the impurity region is formed lateral to the word line drive region rather than between the memory cell array region and the bit line equalization region.
摘要翻译：具有存储单元阵列区域，靠近存储单元阵列的字线驱动区域，与存储单元阵列区域隔开的位线均衡区域的半导体存储器件的布局结构，形成在存储单元阵列区域之间的杂质区域以及电位耦合到位线均衡区域的位线均衡区域，以及在杂质区域上延伸到杂质区域的金属线，该杂质区域向杂质区域提供位线均衡电压，其中连接金属线和杂质区域的接触形成为字线驱动区域而不是在存储单元阵列区域和位线均衡区域之间。

9. 发明授权

US5657265A Semiconductor memory device having circuit array structure for fast operation 失效
标题翻译：具有用于快速操作的电路阵列结构的半导体存储器件
公开(公告)号：US5657265A
公开(公告)日：1997-08-12
申请号：US673001
申请日：1996-07-01
申请人： Jei-Hwan Yoo , Jung-Hwa Lee
发明人： Jei-Hwan Yoo , Jung-Hwa Lee
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/4096 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C7/10 , G11C11/4096
摘要： A semiconductor memory device includes at least four memory cell array blocks, each having an array of memory cells, row and column decoders for selecting a memory cell designated by a row and column address, an I/O line for inputting/outputting data of the memory cell array block, and an I/O driver connected to the I/O line for selectively driving data to/from a selected memory cell. A first data line transmits the data, being connected between the I/O driver of one memory cell array block and the I/O driver of another memory cell array block oppositely arranged with respect to a central portion of the semiconductor memory device. A second data line transmits the data by connecting the first data lines of at least two memory cell array blocks disposed adjacent to each other. A data sense amplifier, connected to the second data line, senses and amplifies the data, and a data output unit, connected to the data sense amplifier, outputs the amplified data to an external lead frame. Therefore, the present invention has an advantage in that a relatively small layout area in required and a relatively low amount of power is consumed.
摘要翻译：半导体存储器件包括至少四个存储单元阵列块，每个存储单元阵列块具有存储单元阵列，用于选择由行和列地址指定的存储单元的行和列解码器，用于输入/输出数据的数据的I / O线存储单元阵列块和连接到I / O线的I / O驱动器，用于选择性地将数据传送到所选择的存储单元。第一数据线传送连接在一个存储单元阵列块的I / O驱动器和相对于半导体存储器件的中心部分相对布置的另一存储单元阵列块的I / O驱动器之间的数据。第二数据线通过连接彼此相邻布置的至少两个存储单元阵列块的第一数据线来发送数据。连接到第二数据线的数据读出放大器感测并放大数据，连接到数据读出放大器的数据输出单元将放大的数据输出到外部引线框。因此，本发明的优点是消耗了所需的相对小的布局面积和相对低的功率。

10. 发明授权

US06845049B2 Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time 失效
标题翻译：半导体存储器件包括能够产生具有基本恒定的延迟时间的延迟信号的延迟电路
公开(公告)号：US06845049B2
公开(公告)日：2005-01-18
申请号：US10313817
申请日：2002-12-05
申请人： Kyu-Nam Lim , Jei-Hwan Yoo , Young-Gu Kang , Jong-Won Lee , Jae-Yoon Shim
发明人： Kyu-Nam Lim , Jei-Hwan Yoo , Young-Gu Kang , Jong-Won Lee , Jae-Yoon Shim
IPC分类号： G11C11/409 , G11C7/04 , G11C7/06 , G11C7/08 , G11C7/22 , G11C8/08 , G11C7/00
CPC分类号： G11C7/04 , G11C7/06 , G11C7/22 , G11C7/227 , G11C2207/2281
摘要： A semiconductor memory device with a bit line sense enable signal generating circuit is disclosed. The semiconductor memory device includes a word line selection signal generating circuit for generating a word line selection signal for selecting a word line; a delay circuit for generating a delayed signal by delaying a signal to the same extent of time period which is needed for the word line selection signal generating circuit to generate the word line selection signal; and a Schmitt trigger for generating a word line enable detecting signal by receiving an output signal from the delay circuit and that is connected to a power supply voltage which has the same voltage level as the voltage level used to enable the word line. The bit line sense enable signal generating circuit in the present invention occupies a relatively smaller layout area than that of conventional semiconductor memory devices. Furthermore, the generating circuit generates a bit line sense enable signal with constant delay time that is immune from process changes, voltage fluctuations, and temperature fluctuations.
摘要翻译：公开了一种具有位线检测使能信号发生电路的半导体存储器件。半导体存储器件包括用于产生用于选择字线的字线选择信号的字线选择信号发生电路; 延迟电路，用于通过将信号延迟到所述字线选择信号发生电路产生字线选择信号所需的相同的时间周期来产生延迟信号; 以及施密特触发器，用于通过接收来自延迟电路的输出信号并连接到与用于使能字线的电压电平相同的电压电平的电源电压来产生字线使能检测信号。本发明中的位线检测使能信号发生电路的布局面积比传统的半导体存储器件要小。此外，发生电路产生具有恒定延迟时间的位线检测使能信号，其免受过程变化，电压波动和温度波动的影响。

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