专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130315004A1 SEMICONDUCTOR DEVICE, A METHOD FOR MANUFACTURING THE SAME, AND A SYSTEM HAVING THE SAME 有权
标题翻译：半导体器件，其制造方法和具有该半导体器件的系统
公开(公告)号：US20130315004A1
公开(公告)日：2013-11-28
申请号：US13833740
申请日：2013-03-15
申请人： Yong Gyu Chu , Hyo Soon Kang , Seung Bum KO , Sang Jae Rhee
发明人： Yong Gyu Chu , Hyo Soon Kang , Seung Bum KO , Sang Jae Rhee
IPC分类号： G11C7/10 , H01L23/48 , H01L21/50
CPC分类号： G11C7/10 , G11C7/1012 , G11C7/1045 , G11C7/22 , G11C2207/105 , H01L21/50 , H01L23/48 , H01L23/50 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/06155 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2924/1434
摘要： A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.
摘要翻译：半导体器件包括存储单元阵列，焊盘组，第一可选焊盘，第二可选焊盘和数据输入多路复用器块，其被配置为基于是否通过全部或部分焊盘组输入数据到存储器单元阵列所述第一可选焊盘和接地彼此连接，其中所述数据输入多路复用器块被配置为基于所述焊盘组中的所述第二焊盘组或所述焊盘组中的第二焊盘组作为所述焊盘组的一部分来选择所述焊盘组中的第一焊盘组，选项板和地面相互连接。

2. 发明申请

US20050114064A1 Circuit for a parallel bit test of a semiconductor memory device and method thereof 审中-公开
标题翻译：半导体存储器件的并行位测试电路及其方法
公开(公告)号：US20050114064A1
公开(公告)日：2005-05-26
申请号：US10911503
申请日：2004-08-05
申请人： Joo-weon Shin , Byung-chul Kim , Seung-bum Ko , Soo-in Cho
发明人： Joo-weon Shin , Byung-chul Kim , Seung-bum Ko , Soo-in Cho
IPC分类号： G11C29/00 , G01D3/00 , G11C29/34
CPC分类号： G11C29/34 , G11C2029/2602
摘要： A method for performing a parallel bit test of a semiconductor memory device, including writing data to each of a plurality of memory cells, reading data from each of the plurality of memory cells, testing the data from each of the plurality of memory cells in a first test mode, and testing the data from each of the plurality of memory cells in a second test mode. A circuit including a first test mode circuit for receiving first data, a second test mode circuit for receiving second data, and wherein the first test mode circuit tests the received first data and the second test mode tests the received second data. Another circuit including a first comparator with a plurality of comparison circuits, a test mode selector for selecting at least one of a plurality of outputs from the first comparator, and a second comparator for receiving the selected output.
摘要翻译：一种用于执行半导体存储器件的并行位测试的方法，包括将数据写入多个存储器单元中的每一个，从多个存储器单元中的每一个读取数据，在多个存储单元中的每一个存储单元中测试数据第一测试模式，并且在第二测试模式中测试来自多个存储器单元中的每一个的数据。一种电路，包括用于接收第一数据的第一测试模式电路，用于接收第二数据的第二测试模式电路，并且其中第一测试模式电路测试接收的第一数据，第二测试模式测试接收的第二数据。另一个电路包括具有多个比较电路的第一比较器，用于选择来自第一比较器的多个输出中的至少一个的测试模式选择器，以及用于接收所选输出的第二比较器。

3. 发明授权

US06496443B2 Data buffer control circuits, integrated circuit memory devices and methods of operation thereof using read cycle initiated data buffer clock signals 失效
标题翻译：数据缓冲器控制电路，集成电路存储器件及其使用读周期启动的数据缓冲时钟信号的操作方法
公开(公告)号：US06496443B2
公开(公告)日：2002-12-17
申请号：US09726197
申请日：2000-11-29
申请人： Byung-Chul Kim , Seung Bum Ko
发明人： Byung-Chul Kim , Seung Bum Ko
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/108
摘要： A data buffer control circuit provides a buffer clock signal to a data buffer of an integrated circuit memory device having a read cycle that is initiated by assertion of a read cycle control signal. A clock buffer circuit that receives an input clock signal and a clock buffer control signal, the clock buffer circuit operative to generate the buffer clock signal from the input clock signal when the clock buffer control signal is in a first state and to prevent generation of the buffer clock signal from the input clock signal when the clock buffer control signal is in a second state. A clock buffer control circuit is responsive to the read cycle control signal and to the clock signal and transitions the clock buffer control signal to the first state responsive to a first transition of the input clock signal following assertion of the read cycle control signal and that transitions the clock buffer control signal to the second state responsive to the end of the predetermined interval. A first half cycle of the input clock signal may commence with the first transition of the input clock signal, and the clock buffer control circuit may be operative to transition the clock buffer control signal to the first state following the first transition of the input clock signal and before the end of the first half cycle of the input clock signal.
摘要翻译：数据缓冲器控制电路将缓冲时钟信号提供给具有通过断言读周期控制信号启动的读周期的集成电路存储器件的数据缓冲器。时钟缓冲器电路，其接收输入时钟信号和时钟缓冲器控制信号，所述时钟缓冲器电路在时钟缓冲器控制信号处于第一状态时从输入时钟信号产生缓冲时钟信号，并且防止产生当时钟缓冲器控制信号处于第二状态时，来自输入时钟信号的缓冲时钟信号。时钟缓冲器控制电路响应于读周期控制信号和时钟信号，并且响应于在读周期控制信号的断言之后的输入时钟信号的第一转变而将时钟缓冲器控制信号转变到第一状态，时钟缓冲器控制信号响应于预定间隔的结束而处于第二状态。输入时钟信号的前半周期可以从输入时钟信号的第一次转变开始，并且时钟缓冲器控制电路可操作以在时钟缓冲器控制信号转换到第一状态之后，在输入时钟信号的第一次转换之后并在输入时钟信号的前半周期结束之前。

4. 发明授权

US06944069B2 Semiconductor memory device having column select line driving scheme for reducing skew between column select lines and column select line driving method thereof 失效
标题翻译：具有用于减少列选择线之间的偏斜的列选择线驱动方案的半导体存储器件及其列选择线驱动方法
公开(公告)号：US06944069B2
公开(公告)日：2005-09-13
申请号：US10803845
申请日：2004-03-18
申请人： Byung-chul Kim , Seung-bum Ko
发明人： Byung-chul Kim , Seung-bum Ko
IPC分类号： G11C11/4094 , G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1048 , G11C11/4096 , G11C2207/002
摘要： Provided are a semiconductor memory device with a column select line (CSL) driving scheme capable of reducing skew between column select lines, and a CSL driving method. The semiconductor memory device includes a plurality of CSL enable controllers and a plurality of CSL disable controllers that are installed around corresponding CSL drivers, thereby making loads on input terminals of the CSL drivers almost the same and reducing enable and disable skew between the CSLs. The semiconductor memory device includes a plurality of enable master signal delayers that delay a signal output from a CSL enable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL enable controllers, and a plurality of disable master signal delayers that delay a signal output from a CSL disable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL disable controllers. It is possible to compensate for signal delay caused by different loads on signal transmission lines and further reduce enable and disable skew between the CSLs.
摘要翻译：提供了具有能够减少列选择线之间的偏斜的列选择线（CSL）驱动方案的半导体存储器件以及CSL驱动方法。半导体存储器件包括多个CSL使能控制器和多个安装在相应的CSL驱动器周围的CSL禁用控制器，从而使得CSL驱动器的输入端子上的负载几乎相同，并且减少了使能和禁止CSL之间的偏移。半导体存储器件包括多个使能主信号延迟器，其延迟从CSL使能主信号发生器输出的信号不同的时间，以产生不同的延迟信号并将延迟信号发送到多个CSL使能控制器，并且多个禁止主信号延迟器，其延迟来自CSL禁用主信号发生器的信号的不同时间，以产生不同的延迟信号并将延迟信号发送到多个CSL禁用控制器。可以补偿由信号传输线路上的不同负载引起的信号延迟，并进一步减少CSL之间的使能和禁止偏移。

5. 发明申请

US20070171763A1 CIRCUIT AND METHOD FOR CONTROLLING WRITE RECOVERY TIME IN SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于控制半导体存储器件中的写恢复时间的电路和方法
公开(公告)号：US20070171763A1
公开(公告)日：2007-07-26
申请号：US11625597
申请日：2007-01-22
申请人： Han-Gyun JUNG , Seung-Bum KO
发明人： Han-Gyun JUNG , Seung-Bum KO
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C11/4076
摘要： A circuit and a method for controlling a write recovery time (tWR) in a semiconductor memory device are disclosed. The method according to one embodiment of the present invention includes receiving an automatic precharge write command, and generating a tWR control signal, which is delayed from a point in time when the automatic precharge write command is received to a point in time when a last data segment is written in the semiconductor memory device. Therefore, power consumption and clock noise may be reduced since an operation of a counter in the circuit for controlling the tWR may be minimized after a point in time when the last data is written.
摘要翻译：公开了一种用于控制半导体存储器件中的写恢复时间（tWR）的电路和方法。根据本发明的一个实施例的方法包括接收自动预充电写入命令，以及生成从接收到自动预充电写入命令的时间点延迟到最后数据的时间点的tWR控制信号片段被写入半导体存储器件中。因此，由于在写入最后数据的时间点之后，用于控制tWR的电路中的计数器的操作可能被最小化，所以能够降低功耗和时钟噪声。

6. 发明授权

US08045404B2 Semiconductor memory device capable of preventing damage to a bitline during a data masking operation 有权
标题翻译：半导体存储器件能够在数据屏蔽操作期间防止对位线的损坏
公开(公告)号：US08045404B2
公开(公告)日：2011-10-25
申请号：US12660439
申请日：2010-02-26
申请人： Byung-Hyun Lee , Byung-Sik Moon , Seung-Bum Ko
发明人： Byung-Hyun Lee , Byung-Sik Moon , Seung-Bum Ko
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C11/4087 , G11C2207/002
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列具有耦合在多个字线和多个位线对之间的多个存储器单元，位线选择电路被配置为在所选择的位线对和本地输入/ 响应于列选择信号的输出线对;本地全局输入/输出门电路，被配置为响应于局部全局输入/输出选择信号在本地输入/输出线对与全局输入/输出线对之间传输数据以及控制器，被配置为驱动字线，将具有第一电压电平的列选择信号输出到位线选择电路，并输出具有低于第一电压的第二电压电平的局部全局输入/输出选择信号响应于外部地址信号和外部命令，电平到本地全局输入/输出门电路。

7. 发明授权

US07675797B2 CAS latency circuit and semiconductor memory device including the same 有权
标题翻译： CAS延迟电路和包括其的半导体存储器件
公开(公告)号：US07675797B2
公开(公告)日：2010-03-09
申请号：US11928022
申请日：2007-10-30
申请人： Byung-hoon Jeong , Seung-bum Ko , Jeong-suk Yang
发明人： Byung-hoon Jeong , Seung-bum Ko , Jeong-suk Yang
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.
摘要翻译：本发明的实施例提供了一种在高速半导体存储器件中产生稳定等待时间信号的列地址选通（CAS）延迟电路，以及包括CAS等待电路的半导体存储器件。 CAS等待时间电路可以包括内部读命令信号发生器和耦合到等待时间信号发生器的等待时钟发生器。在本发明的一个实施例中，等待时间信号发生器通过基于从等待时钟发生器输出的等待时间控制时钟移位从内部读取命令信号发生器输出的内部读取信号来输出稳定的等待时间信号。

8. 发明授权

US07495973B2 Circuit and method for controlling write recovery time in semiconductor memory device 有权
标题翻译：用于控制半导体存储器件中的写恢复时间的电路和方法
公开(公告)号：US07495973B2
公开(公告)日：2009-02-24
申请号：US11625597
申请日：2007-01-22
申请人： Han-Gyun Jung , Seung-Bum Ko
发明人： Han-Gyun Jung , Seung-Bum Ko
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C11/4076
摘要： A circuit and a method for controlling a write recovery time (tWR) in a semiconductor memory device are disclosed. The method according to one embodiment of the present invention includes receiving an automatic precharge write command, and generating a tWR control signal, which is delayed from a point in time when the automatic precharge write command is received to a point in time when a last data segment is written in the semiconductor memory device. Therefore, power consumption and clock noise may be reduced since an operation of a counter in the circuit for controlling the tWR may be minimized after a point in time when the last data is written.
摘要翻译：公开了一种用于控制半导体存储器件中的写恢复时间（tWR）的电路和方法。根据本发明的一个实施例的方法包括接收自动预充电写入命令，以及生成从接收到自动预充电写入命令的时间点延迟到最后数据的时间点的tWR控制信号片段被写入半导体存储器件中。因此，由于在写入最后数据的时间点之后，用于控制tWR的电路中的计数器的操作可能被最小化，所以能够降低功耗和时钟噪声。

9. 发明申请

US20080049526A1 SEMICONDUCTOR MEMORY DEVICE WITH DATA AND LOCAL REDUNDANCY MEMORY CELL ARRAYS, AND REDUNDANCY METHOD THEREOF 审中-公开
标题翻译：具有数据和本地冗余存储器单元阵列的半导体存储器件及其冗余方法
公开(公告)号：US20080049526A1
公开(公告)日：2008-02-28
申请号：US11829854
申请日：2007-07-27
申请人： Han-Gyun JUNG , Seung-Bum KO , Nak-Won HEO
发明人： Han-Gyun JUNG , Seung-Bum KO , Nak-Won HEO
IPC分类号： G11C29/24
CPC分类号： G11C29/846 , G11C29/81
摘要： A semiconductor memory device includes both a data redundancy memory cell array and a local redundancy memory cell array. Cells of the data redundancy memory cell array and/or cells the local redundancy memory cell arrays may be substituted for one or more defective cells of a normal memory cell array, depending on the number of defects generated in the normal memory cell array. An embodiment of a semiconductor memory device may include a plurality of normal memory blocks, each normal memory block comprising a normal memory cell array and a local redundancy memory cell array, at least one data line redundancy memory block, each data line redundancy memory block comprising a data redundancy memory cell array, and a redundancy controller to substitute columns of the data line redundancy memory cell array for some columns of at least two columns in each normal memory cell array, and to substitute columns of the local redundancy memory cell array for the remaining columns of the at least two columns.
摘要翻译：半导体存储器件包括数据冗余存储单元阵列和本地冗余存储单元阵列。取决于在正常存储单元阵列中产生的缺陷的数量，数据冗余存储单元阵列的单元和/或单元本地冗余存储单元阵列可以代替正常存储单元阵列的一个或多个有缺陷单元。半导体存储器件的实施例可以包括多个正常存储器块，每个常规存储器块包括正常存储器单元阵列和局部冗余存储单元阵列，至少一个数据线冗余存储块，每个数据线冗余存储块包括数据冗余存储单元阵列和冗余控制器，用于将数据线冗余存储单元阵列的列替换为每个常规存储单元阵列中的至少两列的一些列，并且将本地冗余存储单元阵列的列替换为至少两列的剩余列。

10. 发明申请

US20100226187A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20100226187A1
公开(公告)日：2010-09-09
申请号：US12660439
申请日：2010-02-26
申请人： Byung-Hyun Lee , Byung-Sik Moon , Seung-Bum Ko
发明人： Byung-Hyun Lee , Byung-Sik Moon , Seung-Bum Ko
IPC分类号： G11C7/00 , G11C8/08 , G11C5/14
CPC分类号： G11C7/18 , G11C11/4087 , G11C2207/002
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列具有耦合在多个字线和多个位线对之间的多个存储器单元，位线选择电路被配置为在所选择的位线对和本地输入/ 响应于列选择信号的输出线对;本地全局输入/输出门电路，被配置为响应于局部全局输入/输出选择信号在本地输入/输出线对与全局输入/输出线对之间传输数据以及控制器，被配置为驱动字线，将具有第一电压电平的列选择信号输出到位线选择电路，并输出具有低于第一电压的第二电压电平的局部全局输入/输出选择信号响应于外部地址信号和外部命令，电平到本地全局输入/输出门电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式