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1. 发明申请

US20050114064A1 Circuit for a parallel bit test of a semiconductor memory device and method thereof 审中-公开
标题翻译：半导体存储器件的并行位测试电路及其方法
公开(公告)号：US20050114064A1
公开(公告)日：2005-05-26
申请号：US10911503
申请日：2004-08-05
申请人： Joo-weon Shin , Byung-chul Kim , Seung-bum Ko , Soo-in Cho
发明人： Joo-weon Shin , Byung-chul Kim , Seung-bum Ko , Soo-in Cho
IPC分类号： G11C29/00 , G01D3/00 , G11C29/34
CPC分类号： G11C29/34 , G11C2029/2602
摘要： A method for performing a parallel bit test of a semiconductor memory device, including writing data to each of a plurality of memory cells, reading data from each of the plurality of memory cells, testing the data from each of the plurality of memory cells in a first test mode, and testing the data from each of the plurality of memory cells in a second test mode. A circuit including a first test mode circuit for receiving first data, a second test mode circuit for receiving second data, and wherein the first test mode circuit tests the received first data and the second test mode tests the received second data. Another circuit including a first comparator with a plurality of comparison circuits, a test mode selector for selecting at least one of a plurality of outputs from the first comparator, and a second comparator for receiving the selected output.
摘要翻译：一种用于执行半导体存储器件的并行位测试的方法，包括将数据写入多个存储器单元中的每一个，从多个存储器单元中的每一个读取数据，在多个存储单元中的每一个存储单元中测试数据第一测试模式，并且在第二测试模式中测试来自多个存储器单元中的每一个的数据。一种电路，包括用于接收第一数据的第一测试模式电路，用于接收第二数据的第二测试模式电路，并且其中第一测试模式电路测试接收的第一数据，第二测试模式测试接收的第二数据。另一个电路包括具有多个比较电路的第一比较器，用于选择来自第一比较器的多个输出中的至少一个的测试模式选择器，以及用于接收所选输出的第二比较器。

2. 发明授权

US06944069B2 Semiconductor memory device having column select line driving scheme for reducing skew between column select lines and column select line driving method thereof 失效
标题翻译：具有用于减少列选择线之间的偏斜的列选择线驱动方案的半导体存储器件及其列选择线驱动方法
公开(公告)号：US06944069B2
公开(公告)日：2005-09-13
申请号：US10803845
申请日：2004-03-18
申请人： Byung-chul Kim , Seung-bum Ko
发明人： Byung-chul Kim , Seung-bum Ko
IPC分类号： G11C11/4094 , G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1048 , G11C11/4096 , G11C2207/002
摘要： Provided are a semiconductor memory device with a column select line (CSL) driving scheme capable of reducing skew between column select lines, and a CSL driving method. The semiconductor memory device includes a plurality of CSL enable controllers and a plurality of CSL disable controllers that are installed around corresponding CSL drivers, thereby making loads on input terminals of the CSL drivers almost the same and reducing enable and disable skew between the CSLs. The semiconductor memory device includes a plurality of enable master signal delayers that delay a signal output from a CSL enable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL enable controllers, and a plurality of disable master signal delayers that delay a signal output from a CSL disable master signal generator for different times so as to generate different delay signals and transmit the delay signals to the plurality of CSL disable controllers. It is possible to compensate for signal delay caused by different loads on signal transmission lines and further reduce enable and disable skew between the CSLs.
摘要翻译：提供了具有能够减少列选择线之间的偏斜的列选择线（CSL）驱动方案的半导体存储器件以及CSL驱动方法。半导体存储器件包括多个CSL使能控制器和多个安装在相应的CSL驱动器周围的CSL禁用控制器，从而使得CSL驱动器的输入端子上的负载几乎相同，并且减少了使能和禁止CSL之间的偏移。半导体存储器件包括多个使能主信号延迟器，其延迟从CSL使能主信号发生器输出的信号不同的时间，以产生不同的延迟信号并将延迟信号发送到多个CSL使能控制器，并且多个禁止主信号延迟器，其延迟来自CSL禁用主信号发生器的信号的不同时间，以产生不同的延迟信号并将延迟信号发送到多个CSL禁用控制器。可以补偿由信号传输线路上的不同负载引起的信号延迟，并进一步减少CSL之间的使能和禁止偏移。

3. 发明授权

US07675797B2 CAS latency circuit and semiconductor memory device including the same 有权
标题翻译： CAS延迟电路和包括其的半导体存储器件
公开(公告)号：US07675797B2
公开(公告)日：2010-03-09
申请号：US11928022
申请日：2007-10-30
申请人： Byung-hoon Jeong , Seung-bum Ko , Jeong-suk Yang
发明人： Byung-hoon Jeong , Seung-bum Ko , Jeong-suk Yang
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076
摘要： Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.
摘要翻译：本发明的实施例提供了一种在高速半导体存储器件中产生稳定等待时间信号的列地址选通（CAS）延迟电路，以及包括CAS等待电路的半导体存储器件。 CAS等待时间电路可以包括内部读命令信号发生器和耦合到等待时间信号发生器的等待时钟发生器。在本发明的一个实施例中，等待时间信号发生器通过基于从等待时钟发生器输出的等待时间控制时钟移位从内部读取命令信号发生器输出的内部读取信号来输出稳定的等待时间信号。

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