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31. 发明授权

US07719870B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US07719870B2
公开(公告)日：2010-05-18
申请号：US11976532
申请日：2007-10-25
申请人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
发明人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译：本发明的目的是避免在由选择的字线上的所有存储单元中的选择晶体管导通的存储单元中构成的存储器阵列中的未选择的数据线被驱动，每个存储器单元使用依赖于可变电阻的存储元件和选择晶体管。为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。

32. 发明授权

US07341892B2 Semiconductor memory cell and method of forming same 有权
公开(公告)号：US07341892B2
公开(公告)日：2008-03-11
申请号：US11368603
申请日：2006-03-07
申请人： Hideyuki Matsuoka , Kiyoo Itoh , Motoyasu Terao , Satoru Hanzawa , Takeshi Sakata
发明人： Hideyuki Matsuoka , Kiyoo Itoh , Motoyasu Terao , Satoru Hanzawa , Takeshi Sakata
IPC分类号： H01L21/82
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

33. 发明申请

US20080049481A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080049481A1
公开(公告)日：2008-02-28
申请号：US11877310
申请日：2007-10-23
申请人： Satoru Hanzawa , Takeshi Sakata , Kazuhiko Kajgaya
发明人： Satoru Hanzawa , Takeshi Sakata , Kazuhiko Kajgaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译：有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

34. 发明授权

US07116593B2 Storage device 有权
标题翻译：储存设备
公开(公告)号：US07116593B2
公开(公告)日：2006-10-03
申请号：US10485566
申请日：2002-09-13
申请人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
发明人： Satoru Hanzawa , Kiyoo Itoh , Hideyuki Matsuoka , Motoyasu Terao , Takeshi Sakata
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译：本发明的目的是避免在由存储单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时，根据可变电阻使用存储元件和选择晶体管进行。为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。

35. 发明申请

US20050265068A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050265068A1
公开(公告)日：2005-12-01
申请号：US11134476
申请日：2005-05-23
申请人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
IPC分类号： H01L27/108 , G11C11/24 , G11C11/405 , G11C11/4097 , H01L21/8242 , H01L27/02
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译：提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。当访问存储器单元时，两个晶体管被激活并且读取该信息。当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

36. 发明授权

US06771535B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06771535B2
公开(公告)日：2004-08-03
申请号：US10412423
申请日：2003-04-14
申请人： Takeshi Sakata , Satoru Hanzawa , Hideyuki Matsuoka , Katsuro Watanabe , Kenchi Ito
发明人： Takeshi Sakata , Satoru Hanzawa , Hideyuki Matsuoka , Katsuro Watanabe , Kenchi Ito
IPC分类号： G11C1100
CPC分类号： H01L27/226 , B82Y10/00 , G11C11/16
摘要： Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the-amplified current to an associated read data line.
摘要翻译：公开了一种快速，高度集成和高可靠性的磁阻随机存取存储器（MRAM）和使用MRAM的半导体器件。半导体器件使用存储单元执行MRAM的读出操作，用于通过使用具有高S / N比的磁性隧道结（MTJ）元件的磁阻的变化来存储信息。每个存储单元包括MTJ元件和双极晶体管。通过选择字线，通过双极晶体管放大在目标存储单元的MTJ元件中流动的电流并将放大的电流输出到相关联的读取数据线来执行读出操作。

37. 发明授权

US06683813B2 Semiconductor memory device equipped with dummy cells 有权
标题翻译：装有虚拟电池的半导体存储器件
公开(公告)号：US06683813B2
公开(公告)日：2004-01-27
申请号：US10315938
申请日：2002-12-11
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C702
CPC分类号： G11C11/4099 , G11C7/14
摘要： There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is comprised of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integration and a lower electrical power as compared with those of the prior art device can be realized.
摘要翻译：提供了用于读出具有放大能力的存储单元的操作的参考电压产生方法和虚拟单元。存储单元包括读取NMOS晶体管，写入晶体管和耦合电容。虚拟单元被制成使得两个存储单元串联连接。每个数据线的最远端布置在相对于读出放大器的虚拟单元。通过使存储单元的读取NMOS晶体管和虚设单元中的每一个中流动的电流量的差异来产生参考电压。结果，可以实现与现有技术的装置相比显示更高速度，更高集成度和更低电力的DRAM。

38. 发明授权

US06335901B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06335901B1
公开(公告)日：2002-01-01
申请号：US09531467
申请日：2000-03-20
申请人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
发明人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.
摘要翻译：响应于外部端子（OPT）的第一状态，SDRAM将其操作模式选择为SDR模式，从而释放已经从存储器读出的数据，以响应于由时钟产生的时钟信号再生电路具有响应于外部端子（OPT）的第二状态而比较电路的输入和输出的相位或选择为DDR模式的功能，从而释放从响应于与外部时钟信号同步的由时钟信号发生电路产生的时钟信号，存储器垫。

39. 发明授权

US06205086B1 Phase control circuit, semiconductor device and semiconductor memory 有权
标题翻译：相位控制电路，半导体器件和半导体存储器
公开(公告)号：US06205086B1
公开(公告)日：2001-03-20
申请号：US09560724
申请日：2000-04-28
申请人： Satoru Hanzawa , Takeshi Sakata , Osamu Nagashima
发明人： Satoru Hanzawa , Takeshi Sakata , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/22 , G11C7/222
摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).
摘要翻译：相位控制电路包括分别向第一时钟信号（BDA1）分配不同的预定延迟时间的多个固定延迟电路（200-0至200-5）;接收从多个时钟信号输出的时钟信号的检测电路（201）的固定延迟电路和与其中的第一时钟信号不同的第二时钟信号（PCLK），并产生以多个位表示的检测信号（202），每个位对应于第一时钟信号和第二时钟之间的相位差信号和可变延迟电路（200-6），其将与每个检测到的信号相对应的相位差延迟到第三时钟信号（BDA2）。

40. 发明授权

US6166990A Clock reproduction circuit that can reproduce internal clock signal correctly in synchronization with external clock signal 有权
标题翻译：时钟再现电路可以与外部时钟信号同步正确地再现内部时钟信号
公开(公告)号：US6166990A
公开(公告)日：2000-12-26
申请号：US332143
申请日：1999-06-14
申请人： Tsukasa Ooishi , Satoru Hanzawa , Kiyoshi Nakatsuka
发明人： Tsukasa Ooishi , Satoru Hanzawa , Kiyoshi Nakatsuka
IPC分类号： G11C11/413 , G11C7/22 , G11C8/18 , G11C11/407 , G11C11/4076 , G11C11/417 , H01L21/822 , H01L27/04 , G11C8/00
CPC分类号： G11C7/22 , G11C8/18 , G11C11/4076
摘要： A frequency determination circuit generating a clock signal phase-locking with an external clock signal at a coarse precision and a fine adjust circuit generating an internal synchronizing signal phase-locking with the external clock signal at a fine precision are provided. The fine adjust circuit has a function of adjusting the phase of the frequency determination circuit when phase synchronization is to be carried out exceeding the adjust range thereof. The frequency determination circuit and the fine adjust circuit receive a clock power supply voltage. A clock reproduction circuit is provided which generates an internal clock signal phase-locking with an external clock signal or a reference clock signal stably even when the operating environment changes.
摘要翻译：提供了以粗精度产生具有外部时钟信号的时钟信号相位锁定的频率确定电路和以外部时钟信号以精确的精度产生内部同步信号锁相的微调电路。微调电路具有当要执行超过其调整范围的相位同步时调节频率确定电路的相位的功能。频率确定电路和微调电路接收时钟电源电压。提供了一种时钟再现电路，即使当操作环境改变时也能稳定地产生与外部时钟信号或参考时钟信号相位锁定的内部时钟信号。

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