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1. 发明授权

US6166990A Clock reproduction circuit that can reproduce internal clock signal correctly in synchronization with external clock signal 有权
标题翻译：时钟再现电路可以与外部时钟信号同步正确地再现内部时钟信号
公开(公告)号：US6166990A
公开(公告)日：2000-12-26
申请号：US332143
申请日：1999-06-14
申请人： Tsukasa Ooishi , Satoru Hanzawa , Kiyoshi Nakatsuka
发明人： Tsukasa Ooishi , Satoru Hanzawa , Kiyoshi Nakatsuka
IPC分类号： G11C11/413 , G11C7/22 , G11C8/18 , G11C11/407 , G11C11/4076 , G11C11/417 , H01L21/822 , H01L27/04 , G11C8/00
CPC分类号： G11C7/22 , G11C8/18 , G11C11/4076
摘要： A frequency determination circuit generating a clock signal phase-locking with an external clock signal at a coarse precision and a fine adjust circuit generating an internal synchronizing signal phase-locking with the external clock signal at a fine precision are provided. The fine adjust circuit has a function of adjusting the phase of the frequency determination circuit when phase synchronization is to be carried out exceeding the adjust range thereof. The frequency determination circuit and the fine adjust circuit receive a clock power supply voltage. A clock reproduction circuit is provided which generates an internal clock signal phase-locking with an external clock signal or a reference clock signal stably even when the operating environment changes.
摘要翻译：提供了以粗精度产生具有外部时钟信号的时钟信号相位锁定的频率确定电路和以外部时钟信号以精确的精度产生内部同步信号锁相的微调电路。微调电路具有当要执行超过其调整范围的相位同步时调节频率确定电路的相位的功能。频率确定电路和微调电路接收时钟电源电压。提供了一种时钟再现电路，即使当操作环境改变时也能稳定地产生与外部时钟信号或参考时钟信号相位锁定的内部时钟信号。

2. 发明授权

US4808857A Sense amplifier circuit for switching plural inputs at low power 失效
标题翻译：用于以低功率切换多个输入的感测放大器电路
公开(公告)号：US4808857A
公开(公告)日：1989-02-28
申请号：US203608
申请日：1988-06-02
申请人： Atsushi Naito , Kiyoshi Nakatsuka , Takashi Inui , Tomohiro Suzuki
发明人： Atsushi Naito , Kiyoshi Nakatsuka , Takashi Inui , Tomohiro Suzuki
IPC分类号： H03K3/02 , G11C7/06 , G11C11/401 , G11C11/409 , G11C11/419 , H03F3/45 , H03K3/356 , H03K5/02 , H03K19/094 , H03K17/693
CPC分类号： H03K3/35606 , G11C7/062
摘要： A sense amplifier circuit is described for switching plural inputs at high speed. At least two transistors for providing at least two true input signals are connected in parallel and have their source terminals connected to a common node from which an output signal may be read. Similarly, at least two other transistors for providing the inverse of the true input signals are connected in parallel and their source terminals are connected to another common node from which an inverse of the output signal may be read. The common nodes are then precharged to the same voltage. True and inverse input signals are applied to their respective transistors through transfer gates where all the true input signals are greater than their respective inverse signals. Therefore, the on-resistance of each of the transistors to which a true input is applied have a higher on-resistance than the associated transistors to which an inverse input is applied. Current flow then rapidly decreases through the transistors transmitting the inverse input signal as current is switchably applied to the transistors transmitting the true input signals.
摘要翻译：描述了用于高速切换多个输入的读出放大器电路。用于提供至少两个真实输入信号的至少两个晶体管并联连接，并且它们的源极端子连接到可从其读取输出信号的公共节点。类似地，用于提供真实输入信号的反相的至少两个其他晶体管并联连接，并且它们的源极端子连接到另一个公共节点，从该公共节点可以读取输出信号的反相。然后将公共节点预充电到相同的电压。真和反输入信号通过传输门施加到它们各自的晶体管，其中所有的真实输入信号都大于它们各自的反相信号。因此，施加真实输入的每个晶体管的导通电阻具有比施加反相输入的相关联的晶体管更高的导通电阻。随着电流可切换地施加到传输真实输入信号的晶体管，电流随后通过反相输入信号传输的晶体管迅速减小。

3. 发明授权

US5055717A Data selector circuit and method of selecting format of data output from plural registers 失效
标题翻译：数据选择电路及从多个寄存器输出数据格式的方法
公开(公告)号：US5055717A
公开(公告)日：1991-10-08
申请号：US398339
申请日：1989-08-24
申请人： Atsushi Naito , Kiyoshi Nakatsuka , Seiichi Yamamoto , Takashi Inui , Tomohiro Suzuki
发明人： Atsushi Naito , Kiyoshi Nakatsuka , Seiichi Yamamoto , Takashi Inui , Tomohiro Suzuki
IPC分类号： G09G5/395 , G11C7/10
CPC分类号： G11C7/1075 , G09G5/395 , G11C7/103
摘要： Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data. Upon decoding the serial sequence selection data of the partial address buffer, a plurality of MOS transistors included in the selector portion are rendered conductive in sequence in response to respective control signals applied to the gates thereof to connect the plurality of data registers via their output buffers to respective output drivers in a sequence determined by the decoded selection data of the partial address buffer for serial data output in the selected serial data output sequence.
摘要翻译：数据选择器电路包括通过相应的输出缓冲器并行连接到多个输出驱动器的多个数据寄存器，其中解码器和选择器部分插在输出缓冲器和输出驱动器之间，用于选择性地提供多个串行数据输出从数据寄存器到输出驱动器的序列，而不是否则将发生的多个数据寄存器的并行数据输出格式。解码器和选择器部分由具有串行序列选择数据的部分地址缓冲器控制。在对部分地址缓冲器的串行序列选择数据进行解码时，响应于施加到其栅极的相应控制信号，包括在选择器部分中的多个MOS晶体管依次被导通，以经由其输出缓冲器连接多个数据寄存器以由所选择的串行数据输出序列中输出的串行数据的部分地址缓冲器的解码选择数据确定的序列分配给相应的输出驱动器。

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