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31. 发明授权

US07271755B2 Resistor ladder interpolation for PGA and DAC 失效
标题翻译： PGA和DAC的电阻梯形图插补
公开(公告)号：US07271755B2
公开(公告)日：2007-09-18
申请号：US10926407
申请日：2004-08-26
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
IPC分类号： H03M1/12 , H03M1/78 , G06F17/17
CPC分类号： H03K17/04106 , H03M1/204 , H03M1/365
摘要： A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
摘要翻译：电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。第一多个开关将各个抽头连接到第一电容器的第二端子。第二多个开关将各个抽头连接到第二电容器的第二端子。通过控制第一和第二多个开关来内插输出电压。

32. 发明授权

US07256725B2 Resistor ladder interpolation for subranging ADC 有权
公开(公告)号：US07256725B2
公开(公告)日：2007-08-14
申请号：US11651454
申请日：2007-01-10
申请人： Jan Mulder
发明人： Jan Mulder
IPC分类号： H03M1/12
CPC分类号： H03K17/04106 , H03F3/45183 , H03F3/45632 , H03F2203/45352 , H03F2203/45354 , H03F2203/45511 , H03M1/204 , H03M1/365
摘要： An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

33. 发明申请

US20070182476A1 ISI reduction technique 有权
标题翻译： ISI缩减技术
公开(公告)号：US20070182476A1
公开(公告)日：2007-08-09
申请号：US11523694
申请日：2006-09-20
申请人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward
发明人： Franciscus Maria Leonardus van der Goes , Jan Mulder , Christopher Michael Ward
IPC分类号： G06G7/18
CPC分类号： H03H19/004
摘要： The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.
摘要翻译：本发明涉及信号处理电路，更具体地说，涉及开关电容器电路以及减少符号间干扰的方法。提供了具有减小的符号间干扰效应的开关电容器电路，包括：电压源，第一电容器，第二电容器和至少一个开关，其被配置为以将第一电容器充电到第一电容器电压，然后通过第二电容器放电，从而减少符号间干扰效应。

34. 发明申请

US20070109173A1 Resistor ladder interpolation for subranging ADC 有权
标题翻译：电阻梯形图插补，用于辅助ADC
公开(公告)号：US20070109173A1
公开(公告)日：2007-05-17
申请号：US11651454
申请日：2007-01-10
申请人： Jan Mulder
发明人： Jan Mulder
IPC分类号： H03M1/12
CPC分类号： H03K17/04106 , H03F3/45183 , H03F3/45632 , H03F2203/45352 , H03F2203/45354 , H03F2203/45511 , H03M1/204 , H03M1/365
摘要： An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.
摘要翻译：模数转换器包括输出多个参考电压的电阻梯形图和接收参考电压的粗略ADC和电压输入。多个粗略比较器接收粗略ADC的输出。开关矩阵接收粗略ADC的输出和参考电压。开关矩阵输入用于选择至少两个电压子范围的多个控制信号。精密ADC接收两个电压子范围和电压输入。多个精细比较器接收精细ADC的输出。编码器将粗略和精细比较器的输出转换为电压输入的数字表示。电压子范围相邻。每个控制信号包括用于控制相应的开关的多个控制线。开关是场效应晶体管。

35. 发明授权

US07208980B2 Comparator with offset compensation 有权
标题翻译：具有偏移补偿的比较器
公开(公告)号：US07208980B2
公开(公告)日：2007-04-24
申请号：US11038386
申请日：2005-01-21
申请人： Jan Mulder
发明人： Jan Mulder
IPC分类号： G01R19/00
CPC分类号： G01R19/16519 , G01R19/16557 , H03F3/45183 , H03F3/45632 , H03F2200/78 , H03F2203/45366 , H03F2203/45644 , H03M1/0607
摘要： A differential comparator with reduced offset. The differential comparator includes a first transistor coupled to a first input current and a second transistor coupled to a second input current. The first and second transistors are biased as diodes during a reset phase to store an offset voltage on parasitic capacitances of the first and second transistors. The first and second transistors are connected together as a latch to provide an output during a latch phase. Drain currents of the first and the second transistors substantially equal the first and the second input currents, respectively, during the reset phase and at the beginning of the latch phase. During the latch phase, currents approximately twice as large as differential-mode signal currents provided by the first and the second input currents are provided to the first and the second transistors, respectively.
摘要翻译：具有减小偏移的差分比较器。差分比较器包括耦合到第一输入电流的第一晶体管和耦合到第二输入电流的第二晶体管。第一和第二晶体管在复位阶段被偏置为二极管，以便在第一和第二晶体管的寄生电容上存储偏移电压。第一和第二晶体管作为锁存器连接在一起以在锁存相位期间提供输出。第一和第二晶体管的漏极电流分别在复位阶段期间和锁存相位开始时基本上等于第一和第二输入电流。在锁存阶段期间，分别向第一和第二晶体管提供大约是由第一和第二输入电流提供的差分模式信号电流的两倍的电流。

36. 发明授权

US07170701B2 Amplifier with a strong output current 失效
标题翻译：放大器具有强大的输出电流
公开(公告)号：US07170701B2
公开(公告)日：2007-01-30
申请号：US10179356
申请日：2002-06-25
申请人： Jan Mulder , Hugo Veenstra , Giuseppe Grillo
发明人： Jan Mulder , Hugo Veenstra , Giuseppe Grillo
IPC分类号： G11B5/09
CPC分类号： G11B5/02 , G11B5/012 , G11B2005/0013 , H03F1/02 , H03F3/3432 , H03F3/4508 , H03F2203/45352
摘要： The present invention relates to an amplifier intended to deliver to a load impedance RL connected between two output terminals of the amplifier an output current Iout which is representative of an input signal (Vin, −Vin) applied to two input terminals of the amplifier, which amplifier includes a first and a second transistor T1 and T2 connected as a differential pair around the load impedance RL. The amplifier according to the invention further includes a third and a fourth transistor T3 and T4 which form a differential pair; degenerated by means of a degenerating impedance Req which has a nominal value equal to that of the load impedance RL of the amplifier, which differential pair (T3, T4) is intended to be controlled by means of a control signal (−Vin/2, Vin/2), in anti-phase with the input signal (Vin, −Vin). The invention permits to double the output current Iout of the amplifier without, however, increasing its power consumption.
摘要翻译：本发明涉及一种放大器，其用于传送到连接在放大器的两个输出端之间的负载阻抗RL，该输出电流Iout表示施加到放大器的两个输入端的输入信号（Vin，-Vin）放大器包括作为负载阻抗RL周围的差分对连接的第一和第二晶体管T 1和T 2。根据本发明的放大器还包括形成差分对的第三和第四晶体管T 3和T 4; 通过衰减阻抗Req退化，该衰减阻抗Req的标称值等于放大器的负载阻抗RL的额定值，该差分对（T 3，T 4）将通过控制信号（-Vin / 2，Vin / 2），与输入信号（Vin，-Vin）反相。本发明允许放大器的输出电流Iout加倍，而不增加其功率消耗。

37. 发明申请

US20060164126A1 High-speed comparator 有权
标题翻译：高速比较器
公开(公告)号：US20060164126A1
公开(公告)日：2006-07-27
申请号：US11038388
申请日：2005-01-21
申请人： Jan Mulder , Franciscus van der Goes , Marcel Lugthart
发明人： Jan Mulder , Franciscus van der Goes , Marcel Lugthart
IPC分类号： G01R19/00
CPC分类号： G01R19/16519 , G01R19/16557 , H03K3/356139 , H03K5/2481 , H03K5/249 , H03M1/0604
摘要： A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.
摘要翻译：差分比较器，具有更低的电源电压，具有改进的误码率性能。差分比较器包括接收差分输入的第一对晶体管。第二对晶体管耦合到第一对晶体管。一对电阻元件连接在第一对和第二对晶体管之间，以增加由第一和第二对晶体管共享的偏置电流。增加的偏置电流减少差分比较器从元稳定状态转变到稳定状态所需的时间，从而提高差分比较器的误码率。电阻元件可以使用线性电阻或传输门。第一或第二对晶体管的栅极可以提供输出。

38. 发明申请

US20050244796A1 Motion simulator with exchangeable unit 审中-公开
标题翻译：具有可更换单元的运动模拟器
公开(公告)号：US20050244796A1
公开(公告)日：2005-11-03
申请号：US11084432
申请日：2005-03-18
申请人： Jan Mulder , Adriaan Beukers , Max Baarspul , Michael Johannes van Tooren , Stefaan Emiel de Winter
发明人： Jan Mulder , Adriaan Beukers , Max Baarspul , Michael Johannes van Tooren , Stefaan Emiel de Winter
IPC分类号： G09B9/04 , G09B9/02
CPC分类号： G09B9/04
摘要： A motion simulator provided with a movable housing, preferably carried by a number of length-adjustable legs, in which housing projection means are arranged for visual information supply, while in the housing a control environment of a motion apparatus to be simulated is situated, the control environment being incorporated in a removable unit, which unit is exchangeable for another, comparable unit having a different control environment to be simulated.
摘要翻译：一种运动模拟器，其具有可移动的壳体，优选地由许多长度可调节的腿部承载，其中壳体突出装置设置用于视觉信息供给，而在壳体中，要被模拟的运动装置的控制环境位于，控制环境被结合在可移动单元中，该单元可交换为具有不同控制环境的另一可比单元。

39. 发明申请

US20050068216A1 Resistor ladder interpolation for PGA and DAC 失效
标题翻译： PGA和DAC的电阻梯形图插补
公开(公告)号：US20050068216A1
公开(公告)日：2005-03-31
申请号：US10926407
申请日：2004-08-26
申请人： Jan Mulder , Franciscus Maria Leonardus Goes , Jan Westra , Rudy Plassche
发明人： Jan Mulder , Franciscus Maria Leonardus Goes , Jan Westra , Rudy Plassche
IPC分类号： H03K17/041 , H03M1/06 , H03M1/14 , H03M1/20 , H03M1/36 , H03M1/78
CPC分类号： H03K17/04106 , H03M1/204 , H03M1/365
摘要： A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
摘要翻译：电压内插电路包括连接在地和电压输入端之间的电阻梯形电阻，并具有多个电阻器，电阻器之间具有电压抽头。放大器（可选地）具有在其相应的第一端子和放大器的输入端连接在一起的第一和第二电容器。第一多个开关将各个抽头连接到第一电容器的第二端子。第二多个开关将各个抽头连接到第二电容器的第二端子。通过控制第一和第二多个开关来内插输出电压。

40. 发明申请

US20050035810A1 Multiplexer with low parasitic capacitance effects 有权
标题翻译：具有低寄生电容效应的多路复用器
公开(公告)号：US20050035810A1
公开(公告)日：2005-02-17
申请号：US10953420
申请日：2004-09-30
申请人： Jan Mulder , Franciscus Maria Leonardus van der Goes
发明人： Jan Mulder , Franciscus Maria Leonardus van der Goes
IPC分类号： H03M1/36 , H03M1/12
CPC分类号： H03K17/002 , H03K17/145 , H03M1/36 , H03M1/365
摘要： A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.
摘要翻译：差分多路复用器包括多个复用电路。每个复用电路输入包括正输入信号和负输入信号的对应差分输入信号，并输出正和负输出信号。每个复用电路包括第一，第二，第三和第四晶体管。第一和第二晶体管输入正输入信号。第三和第四晶体管输入负输入信号。第一和第三晶体管的输出端连接到正输出信号。第二和第四晶体管的输出端连接到负输出信号。正和负输出信号通过第一和第四晶体管上的栅极电压来控制。当使用差分多路复用器时，第二和第三晶体管截止。晶体管交叉耦合以在正输入信号和负输出信号中的正输入信号和负输入信号共模之间产生泄漏。

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