专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US5963049A Programmable logic array integrated circuit architectures 失效
公开(公告)号：US5963049A
公开(公告)日：1999-10-05
申请号：US807561
申请日：1997-02-28
申请人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
发明人： Richard G. Cliff , Francis B. Heile , Joseph Huang , Christopher F. Lane , Fung Fung Lee , Cameron McClintock , David W. Mendel , Ninh D. Ngo , Bruce B. Pedersen , Srinivas T. Reddy , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1736 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/1776
摘要： A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region). Region output signal routing flexibility may also be enhanced to facilitate simultaneous performance of combinatorial logic and a separate "lonely register" function in modules of the regions.

32. 发明授权

US09099999B1 Adjustable drive strength input-output buffer circuitry 有权
标题翻译：可调驱动强度输入输出缓冲电路
公开(公告)号：US09099999B1
公开(公告)日：2015-08-04
申请号：US13485768
申请日：2012-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
IPC分类号： H01L29/73 , H01L29/40 , H03K17/00 , H05K1/18 , H01L25/065 , H01L27/06
CPC分类号： H03K17/00 , H01L25/0652 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2224/16225 , H01L2924/0002 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H05K1/144 , H05K1/181 , H05K2201/045 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00
摘要： An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.
摘要翻译：提供了一种多芯片封装中的集成电路。该集成电路可以包括被配置为与其它片外部件接口的可调节接口电路。特别地，可调接口电路可以包括微控制输入 - 输出缓冲器，其可操作用于驱动离开集成电路的信号，并且可操作以经由微型小型接收器从多芯片封装中的其他集成电路接收信号。微控制输入 - 输出缓冲器可以包括输出缓冲器和输入缓冲器。输出缓冲器可以具有可编程驱动强度，并且可以根据期望的应用选择性地切换和使用。每个输出缓冲器可以包括电平移位器，缓冲电路和多个类似逆变器的电路，每个可以导通或关断以调整该输出缓冲器的驱动强度。

33. 发明申请

US20110227606A1 PROGRAMMABLE HIGH-SPEED INTERFACE 有权
标题翻译：可编程高速接口
公开(公告)号：US20110227606A1
公开(公告)日：2011-09-22
申请号：US13149168
申请日：2011-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03K19/0175 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

34. 发明申请

US20080186056A1 PROGRAMMABLE HIGH-SPEED INTERFACE 有权
标题翻译：可编程高速接口
公开(公告)号：US20080186056A1
公开(公告)日：2008-08-07
申请号：US11830831
申请日：2007-07-30
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03K19/0175
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

35. 发明授权

US07190755B1 Phase-locked loop circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的锁相环电路
公开(公告)号：US07190755B1
公开(公告)日：2007-03-13
申请号：US10266092
申请日：2002-10-04
申请人： Chiakang Sung , Joseph Huang , Bonnie I Wang , Richard G Cliff
发明人： Chiakang Sung , Joseph Huang , Bonnie I Wang , Richard G Cliff
IPC分类号： H03D3/24
CPC分类号： H03K19/1774 , H03K19/177 , H03L7/0891 , H03L7/0996 , H03L7/183
摘要： A phase-locked loop circuit (“PLL”) is adjustable in both phase and frequency. By providing a plurality of taps on the voltage-controlled oscillator of the PLL, and providing separate multiplexers, each of which can select a different tap—one for the PLL feedback loop and one for the PLL output—one allows the user to adjust the phase of the output relative to that of the input. Similarly, by providing loadable pre-scale (divide by N), post-scale (divide by K) and feedback-scale (divide by M) counters, one allows the user to adjust the frequency of the output to be M/(NK) times that of the input.
摘要翻译：锁相环电路（“PLL”）可在相位和频率两个方面调节。通过在PLL的压控振荡器上提供多个抽头，并提供单独的多路复用器，每个复用器可以为PLL反馈回路选择不同的抽头，并为PLL输出选择一个，一个允许用户调整输出的相位相对于输入的相位。类似地，通过提供可加载的预缩放（除以N），后标尺（除以K）和反馈量表（除以M）计数器，允许用户将输出的频率调整为M /（NK ）倍的输入。

36. 发明授权

US06437650B1 Phase-locked loop or delay-locked loop circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的锁相环或延迟锁定环电路
公开(公告)号：US06437650B1
公开(公告)日：2002-08-20
申请号：US09855865
申请日：2001-05-15
申请人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
发明人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
IPC分类号： H03L706
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/0996 , H03L7/0997
摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
摘要翻译：可编程逻辑器件提供有锁相环（“PLL”）或延迟锁定环（“DLL”）电路，其中反馈回路电路在接收的设备上基本平行并复制时钟信号分配网络的一部分主PLL / DLL输出信号。以这种方式，分布式反馈环路更容易地提供对通过PLL / DLL电路服务的时钟信号分配网络传播的信号经历的分布延迟的基本精确的匹配。

37. 发明授权

US06400598B1 Programmable logic integrated circuit devices with low voltage differential signaling capabilities 有权
标题翻译：具有低电压差分信号功能的可编程逻辑集成电路器件
公开(公告)号：US06400598B1
公开(公告)日：2002-06-04
申请号：US09843299
申请日：2001-04-25
申请人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G. Cliff , Joseph Huang , Bonnie I. Wang , Wayne Yeung
发明人： Khai Nguyen , Xiaobao Wang , In Whan Kim , Chiakang Sung , Richard G. Cliff , Joseph Huang , Bonnie I. Wang , Wayne Yeung
IPC分类号： G11C506
CPC分类号： H03K19/17744 , H03K19/018521 , H03K19/1778 , H03K19/17784
摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.
摘要翻译：可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

38. 发明授权

US06346827B1 Programmable logic device input/output circuit configurable as reference voltage input circuit 有权
标题翻译：可编程逻辑器件输入/输出电路可配置为参考电压输入电路
公开(公告)号：US06346827B1
公开(公告)日：2002-02-12
申请号：US09366937
申请日：1999-08-04
申请人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , In Whan Kim
发明人： Wayne Yeung , Chiakang Sung , Myron W. Wong , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang , Joseph Huang , In Whan Kim
IPC分类号： H01L2500
CPC分类号： G11C5/147 , G11C5/066
摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.
摘要翻译：可编程逻辑器件输入/输出引脚的可编程输入/输出电路可以在标准I / O模式或参考电压模式下进行配置。该电路包括可跟踪的标准I / O缓冲器以及参考电压钳位电路。在参考电压模式下，I / O电路被三态化，参考电压钳位电路将参考电压从I / O引脚传递到参考电压总线。在标准I / O模式下，I / O缓冲区可以运行。参考电压钳位电路将I / O引脚与参考电压总线隔离，并可能包括欠压和过压保护，以防止参考电压总线受到超出范围I / O信号的干扰。

39. 发明授权

US06271681B1 PCI-compatible programmable logic devices 有权
标题翻译： PCI兼容的可编程逻辑器件
公开(公告)号：US06271681B1
公开(公告)日：2001-08-07
申请号：US09395886
申请日：1999-09-14
申请人： Richard G. Cliff , Francis B. Heile , Joseph Huang , David W. Mendel , Bruce B. Pedersen , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
发明人： Richard G. Cliff , Francis B. Heile , Joseph Huang , David W. Mendel , Bruce B. Pedersen , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
IPC分类号： H03K19177
CPC分类号： H03K19/1774 , H03K19/17744
摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Regions of programmable logic within the device are closely coupled to the data signal output pins and clock signal input pins such that delay between application of a clock signal to the device and output of a data signal from the device is within PCI signal standards for delay. The device also includes output circuitry that can be configured to selectively invert signals to output enable and data input enable terminals of the output circuitry.
摘要翻译：可编程逻辑集成电路器件具有几个功能，可帮助其根据PCI特殊兴趣组的外设组件接口（“PCI”）信令协议执行。器件内的可编程逻辑区域紧密耦合到数据信号输出引脚和时钟信号输入引脚，使得施加时钟信号与器件之间的延迟和来自器件的数据信号的输出之间的延迟处于用于延迟的PCI信号标准之内。该器件还包括可被配置为选择性地将信号反转到输出电路的输出使能和数据输入使能端的输出电路。

40. 发明授权

US06204688B1 Programmable logic array integrated circuit devices with interleaved logic array blocks 有权
标题翻译：具有交错逻辑阵列块的可编程逻辑阵列集成电路器件
公开(公告)号：US06204688B1
公开(公告)日：2001-03-20
申请号：US09208124
申请日：1998-12-09
申请人： Richard G. Cliff , Francis B. Heile , Joseph Huang , David W. Mendel , Bruce B. Pedersen , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
发明人： Richard G. Cliff , Francis B. Heile , Joseph Huang , David W. Mendel , Bruce B. Pedersen , Chiakang Sung , Kerry Veenstra , Bonnie I. Wang
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/04 , H03K19/17704 , H03K19/17728 , H03K19/17796
摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.
摘要翻译：可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。本地导体也可用于区域内通信，以及相邻区域之间的通信。辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式