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31. 发明授权

US07358768B2 XOR-based conditional keeper and an architecture implementing its application to match lines 有权
标题翻译：基于XOR的条件守护者和实现其应用程序以匹配行的架构
公开(公告)号：US07358768B2
公开(公告)日：2008-04-15
申请号：US11328110
申请日：2006-01-10
申请人： Chung-Hsien Hua , Chi-Wei Peng , Wei Hwang
发明人： Chung-Hsien Hua , Chi-Wei Peng , Wei Hwang
IPC分类号： G06F7/50 , H03K19/21 , H03K19/096
CPC分类号： G11C15/04
摘要： The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed. Further, the XOR-based conditional keeper of the present invention can also apply to all kinds of dynamic circuits, particularly to a high fan-in circuit.
摘要翻译：本发明公开了一种基于XOR的条件跟踪器和实现其应用来匹配线路的架构，其中条件保持器中的异或门接收与CAM（内容可寻址存储器）单元同步的时钟信号，并与浮动信号进行协作节点以产生XOR控制信号，并且XOR控制信号被发送到P型晶体管以创建数据信号以控制基于XOR的条件保持器，使得基于XOR的条件跟踪器可以执行适当的对应动作，其中可以替代仅仅是“开”和“关”模式的传统守护者。此外，本发明的基于XOR的条件跟踪器可以应用于动态CAM匹配线路架构，使得动态匹配线路具有较低的功耗，较高的抗噪声性能和较高的处理速度。此外，本发明的基于XOR的条件保持器也可以应用于各种动态电路，特别是高风扇电路。

32. 发明授权

US07284028B2 Comparator eliminating need for one's complement logic for signed numbers 失效
标题翻译：比较器消除了对符号数字的补码逻辑的需要
公开(公告)号：US07284028B2
公开(公告)日：2007-10-16
申请号：US10287108
申请日：2002-11-01
申请人： Wei Hwang , Kun Wu
发明人： Wei Hwang , Kun Wu
IPC分类号： G06F7/50 , G06F7/02
CPC分类号： G06F7/026
摘要： An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.
摘要翻译：一种用于在包括具有至少一个输入馈送的比较器的计算环境中提供高效率功耗的高速计算能力的装置和方法; 与比较器进行电子通信的符号选择器; 和结果标志发生器与符号选择器和比较器进行电子通信。符号选择器具有输入数据馈送和等效数量的专用指示符，用于从每个输入数据馈送的无符号数中识别有符号数字。结果标志发生器从比较器接收第一个合成的馈送，并从该符号选择器接收第二个合成的馈送。符号选择器可以设计成提供合成输出。在对输入馈送进行集体操作并选择性地在其他馈送（例如符号馈送和Ini馈送）上产生结果输出。

33. 发明授权

US06492227B1 Method for fabricating flash memory device using dual damascene process 失效
标题翻译：使用双镶嵌工艺制造闪存器件的方法
公开(公告)号：US06492227B1
公开(公告)日：2002-12-10
申请号：US09624563
申请日：2000-07-24
申请人： Li-Kong Wang , Louis L. Hsu , Wei Hwang
发明人： Li-Kong Wang , Louis L. Hsu , Wei Hwang
IPC分类号： H01L218234
CPC分类号： H01L21/28273
摘要： A method is provided for fabricating memory devices on a semiconductor substrate using a dual damascene process. The method includes the steps of forming at least one dummy gate structure for at least one memory device on the semiconductor substrate, depositing dielectric material on surroundings of the at least one dummy gate structure, etching the dielectric material and the at least one dummy gate structure to form at least one control gate void and at least one floating gate void, forming a gate dielectric layer on a bottom surface of the at least one floating gate void, depositing floating gate material on the gate dielectric layer in the at least one floating gate void to form a floating gate, depositing a dielectric layer on the floating gate, and depositing control gate material on the dielectric layer in the at least one control gate void to form a control gate. Support devices may be fabricated on the semiconductor substrate by a single damascene process this is integrated with the processes of fabricating the memory devices, so that top surfaces of the support devices and the memory devices are substantially coplanar.
摘要翻译：提供了一种使用双镶嵌工艺在半导体衬底上制造存储器件的方法。该方法包括以下步骤：在半导体衬底上形成用于至少一个存储器件的至少一个虚拟栅极结构，在至少一个虚拟栅极结构的周围沉积介电材料，蚀刻电介质材料和至少一个虚拟栅极结构以形成至少一个控制栅极空隙和至少一个浮置栅极空隙，在所述至少一个浮置栅极空隙的底表面上形成栅极电介质层，在至少一个浮置栅极中的栅极介电层上沉积浮置栅极材料空隙以形成浮置栅极，在浮置栅极上沉积介电层，以及将控制栅极材料沉积在所述至少一个控制栅极中的介电层上以形成控制栅极。可以通过单个镶嵌工艺在半导体衬底上制造支撑装置，其与制造存储器件的工艺集成，使得支撑装置和存储装置的顶表面基本上共面。

34. 发明授权

US06219822B1 Method and system for tuning of components for integrated circuits 失效
标题翻译：用于集成电路组件调谐的方法和系统
公开(公告)号：US06219822B1
公开(公告)日：2001-04-17
申请号：US09129717
申请日：1998-08-05
申请人： George D. Gristede , Wei Hwang , Christophe Robert Tretz
发明人： George D. Gristede , Wei Hwang , Christophe Robert Tretz
IPC分类号： H03K1900
CPC分类号： G06F17/505
摘要： A method for automatically tuning object sizes in an integrated circuit includes the steps of providing a circuit having objects disposed therein, inputting equations associated with the objects to provide a relationship between a size of the object and timing information of signals transmitted between the objects, extracting transition times of the signals transmitted between objects by simulating the circuit in operation by evaluating the equations and adjusting the sizes of the objects in the circuit according to the timing information and the transition times until user defined criteria are achieved for the circuit. Systems are also provided to carry out the method.
摘要翻译：一种用于在集成电路中自动调谐对象尺寸的方法包括以下步骤：提供具有设置在其中的对象的电路，输入与对象相关联的方程，以提供对象的大小与在对象之间传输的信号的定时信息之间的关系，提取通过在运行中模拟电路的运算中的信号的转换时间，并根据定时信息和转换时间调整电路中的对象的大小，直到电路达到用户定义的标准。还提供系统来执行该方法。

35. 发明授权

US5995425A Design of provably correct storage arrays 失效
标题翻译：可靠的存储阵列设计
公开(公告)号：US5995425A
公开(公告)日：1999-11-30
申请号：US898826
申请日：1997-07-23
申请人： Walter Harvey Henkels, deceased , Wei Hwang , Rajiv Vasant Joshi , Albert Thomas Williams
发明人： Walter Harvey Henkels, deceased , Wei Hwang , Rajiv Vasant Joshi , Albert Thomas Williams
IPC分类号： G01R31/3185 , G11C7/00
CPC分类号： G01R31/318536 , Y10S257/903
摘要： A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. Using the elimination process for elements which are difficult to be extracted in Boolean form the logic around and inside a memory structure can be verified. The resultant register array hardware organization can be verified to all pins and nets up to the storage element.
摘要翻译：硬件设计技术允许检查具有嵌入式阵列和寄存器的大型宏的元素和原理图的设计系统语言（DSL）规范。硬件组织将逻辑验证的CPU时间缩小到指数级数量级，而不会引发验证过程或逻辑仿真。硬件组织由水平字层而不是位级组成。使用布尔形式难以提取的元素的消除过程可以验证存储器结构周围和内部的逻辑。结果寄存器阵列硬件组织可以验证所有引脚和网络直到存储元件。

36. 发明授权

US5973529A Pulse-to-static conversion latch with a self-timed control circuit 失效
标题翻译：具有自定时控制电路的脉冲至静态转换锁存器
公开(公告)号：US5973529A
公开(公告)日：1999-10-26
申请号：US778854
申请日：1997-01-06
申请人： Terry Ivan Chappell , Walter Harvey Henkels , Wei Hwang , Rajiv Vasant Joshi
发明人： Terry Ivan Chappell , Walter Harvey Henkels , Wei Hwang , Rajiv Vasant Joshi
IPC分类号： H03K3/037 , H03K3/289
CPC分类号： H03K3/0375
摘要： A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance.
摘要翻译：公开了一种低功率脉冲到静态转换锁存电路。该电路包括自定时控制和使用自复位CMOS电路技术设计的n位锁存阵列。控制器的自定时功能只需要一个系统时钟输入。评估，复位和写使能控制都在控制宏中生成。锁存器是电平敏感扫描设计（LSSD）兼容的，并符合自复位CMOS（SCRMOS）测试模式。这些锁存器的使用有助于采用静态和动态电路的混合来实现高性能的高级数字系统的同步，流水线操作，电源管理和测试。

37. 发明授权

US5790839A System integration of DRAM macros and logic cores in a single chip architecture 失效
标题翻译：在单芯片架构中系统集成DRAM宏和逻辑内核
公开(公告)号：US5790839A
公开(公告)日：1998-08-04
申请号：US770364
申请日：1996-12-20
申请人： Wing Kin Luk , Wei Hwang
发明人： Wing Kin Luk , Wei Hwang
IPC分类号： G11C11/407 , G11C5/02 , G11C5/14 , G11C11/401 , H01L27/10 , G06F1/10 , G06F1/18
CPC分类号： G11C5/025 , G11C5/14
摘要： A chip architecture standard merges dynamic random access memory (DRAM) macros and logic cores. The standard from merged DRAM and logic design provides the advantages of simplicity, high read and write access rates, lower power dissipation and noise suppression in system-on-chip designs. The architecture depends upon balanced clock distribution for its high performance and low clock skew to the DRAM macros and logic cores. Balanced wirings from output drivers of the control logic to corresponding inputs of the different DRAM macros minimize differences in address and control signal delays. Separated Vdd and Gnd power grids distribute power to the DRAM macros and the logic cores and incorporate decoupling capacitor arrays to provide noise suppression between the DRAM macros and logic and to minimize di/dt power supply fluctuations on chip performance.
摘要翻译：芯片架构标准融合了动态随机存取存储器（DRAM）宏和逻辑核心。合并DRAM和逻辑设计的标准提供了简单，高读写访问速率，降低功耗和降低片上系统设计噪声的优势。该架构取决于平衡时钟分配，因为其高性能和低时钟偏移到DRAM宏和逻辑内核。从控制逻辑的输出驱动器到不同DRAM宏的相应输入的平衡布线最小化地址和控制信号延迟的差异。分离的Vdd和Gnd电源将功率分配给DRAM宏和逻辑内核，并结合去耦电容阵列，以提供DRAM宏和逻辑之间的噪声抑制，并最大限度地减少芯片性能的di / dt电源波动。

38. 发明授权

US5777491A High-performance differential cascode voltage switch with pass gate logic elements 失效
标题翻译：具有通过门逻辑元件的高性能差分共源共栅电压开关
公开(公告)号：US5777491A
公开(公告)日：1998-07-07
申请号：US660836
申请日：1996-06-10
申请人： Wei Hwang , Fang-Shi Jordan Lai
发明人： Wei Hwang , Fang-Shi Jordan Lai
IPC分类号： G06F7/50 , G06F7/508 , H03K19/173 , H03K19/0948
CPC分类号： G06F7/508 , H03K19/1738 , G06F2207/5063
摘要： Performance of a dual cascode voltage switch is improved and floating node effects including charge sharing and ratioing of output voltages are avoided by constituting the true and complement logic trees as pass gates of equal height, preferably limited, where possible, to a single transistor. The logic trees have substantially identical transistor layout configurations and different logic functions are established by selective connection of control and conduction terminals of the pass gates to reference logic level voltages of true and complement input variable signal values.
摘要翻译：改进了双共源共栅电压开关的性能，并且通过将真实和补码逻辑树构成相等高度的通孔来避免包括电荷共享和输出电压的比例的浮动节点效应，在可能的情况下，优选地限于单个晶体管。逻辑树具有基本上相同的晶体管布局配置，并且通过将通孔的控制和导通端子选择性地连接到真实和补码输入可变信号值的参考逻辑电平电压来建立不同的逻辑功能。

39. 发明授权

US5363327A Buried-sidewall-strap two transistor one capacitor trench cell 失效
标题翻译：埋层侧壁带两个晶体管一个电容器沟槽电池
公开(公告)号：US5363327A
公开(公告)日：1994-11-08
申请号：US6087
申请日：1993-01-19
申请人： Henkles, Walter H. , Wei Hwang
发明人： Henkles, Walter H. , Wei Hwang
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10844 , H01L27/108
摘要： A two transistor one capacitor DRAM cell configured with respect to a bit line pair and a single word line in which the gates of the two transistors are connected to the single word line and one of the source/drains of each transistor is connected to a respective electrode of the capacitor and the other of the source/drains of the transistors is connected to a respective bit line of a complementary bit line pair. The storage capacitor is a three dimensional structure with both electrodes being electrically well isolated from electrodes of all other cell storage capacitors. A stacked in trench cell fabrication design is disclosed having a buried strap for connecting the outer electrode to a diffusion region of one transistor and a surface strap for connecting the inner electrode to a diffusion region of the second access transistor.
摘要翻译：相对于位线对和单个字线配置的两晶体管一电容器DRAM单元，其中两个晶体管的栅极连接到单个字线，并且每个晶体管的源极/漏极之一连接到相应的电容器的电极和晶体管的源/漏极中的另一个连接到互补位线对的相应位线。存储电容器是三维结构，其中两个电极与所有其它电池存储电容器的电极电绝缘。公开了一种堆叠的沟槽电池制造设计，其具有用于将外部电极连接到一个晶体管的扩散区域的掩埋带和用于将内部电极连接到第二存取晶体管的扩散区域的表面带。

40. 发明授权

US5075571A PMOS wordline boost cricuit for DRAM 失效
标题翻译：用于DRAM的PMOS字线升压电路
公开(公告)号：US5075571A
公开(公告)日：1991-12-24
申请号：US636840
申请日：1991-01-02
申请人： Sang H. Dhong , Wei Hwang , Yoichi Taira
发明人： Sang H. Dhong , Wei Hwang , Yoichi Taira
IPC分类号： G11C11/407 , G11C11/408 , H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H03K5/02
CPC分类号： H03K5/023 , G11C11/4085
摘要： A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure having one contact coupled to a wordline, a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well about the gate, first and second contacts. An isolating structure is positioned about the N-well to enable it to be a separately controlled from surrounding N-well structures. Pulse circuits are coupled to the transistor for applying, when activated, a potential that enables the wordline to transition to a more negative potential. A bias circuit is also provided for biasing the N-well at a first potential and a second lower potential, the second lower potential applied when the pulse circuits are activated. As a result, body effects in the PMOS transistor are minimized while at the same time enabling a boost potential to be applied to the wordline.

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