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1. 发明授权

US5075571A PMOS wordline boost cricuit for DRAM 失效
标题翻译：用于DRAM的PMOS字线升压电路
公开(公告)号：US5075571A
公开(公告)日：1991-12-24
申请号：US636840
申请日：1991-01-02
申请人： Sang H. Dhong , Wei Hwang , Yoichi Taira
发明人： Sang H. Dhong , Wei Hwang , Yoichi Taira
IPC分类号： G11C11/407 , G11C11/408 , H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H03K5/02
CPC分类号： H03K5/023 , G11C11/4085
摘要： A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure having one contact coupled to a wordline, a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well about the gate, first and second contacts. An isolating structure is positioned about the N-well to enable it to be a separately controlled from surrounding N-well structures. Pulse circuits are coupled to the transistor for applying, when activated, a potential that enables the wordline to transition to a more negative potential. A bias circuit is also provided for biasing the N-well at a first potential and a second lower potential, the second lower potential applied when the pulse circuits are activated. As a result, body effects in the PMOS transistor are minimized while at the same time enabling a boost potential to be applied to the wordline.

2. 发明授权

US5339274A Variable bitline precharge voltage sensing technique for DRAM structures 失效
标题翻译：用于DRAM结构的可变位线预充电电压感测技术
公开(公告)号：US5339274A
公开(公告)日：1994-08-16
申请号：US969644
申请日：1992-10-30
申请人： Sang H. Dhong , Toshiaki Kirihata , Hyun J. Shin , Toshio Sunaga , Yoichi Taira , Lewis M. Terman
发明人： Sang H. Dhong , Toshiaki Kirihata , Hyun J. Shin , Toshio Sunaga , Yoichi Taira , Lewis M. Terman
IPC分类号： G11C11/409 , G11C11/407 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094
摘要： A sensing technique uses a variable precharge voltage sensing with a single bitline swing in a DRAM cell or array of DRAM cells so that the power dissipation is reduced. The bitline precharge voltage varies from one RAS cycle to the next RAS cycle depending upon the level of the data in the accessed cells. Such an arrangement eliminates the need for a reference voltage generator since the precharge voltage is not the same voltage for each RAS cycle.
摘要翻译：感测技术在DRAM单元或DRAM单元阵列中使用单个位线摆动的可变预充电电压感测，从而降低功耗。位线预充电电压根据所访问的单元中的数据的电平而从一个RAS周期到下一个RAS周期变化。这种布置消除了对参考电压发生器的需要，因为对于每个RAS周期，预充电电压不是相同的电压。

3. 发明授权

US5453953A Bandgap voltage reference generator 失效
标题翻译：带隙电压基准发生器
公开(公告)号：US5453953A
公开(公告)日：1995-09-26
申请号：US281236
申请日：1994-07-27
申请人： Sang H. Dhong , Hyun J. Shin , Wei Hwang
发明人： Sang H. Dhong , Hyun J. Shin , Wei Hwang
IPC分类号： G11C11/407 , G11C5/14 , G11C8/08 , H01L21/822 , H01L27/04 , G05F3/24
CPC分类号： G11C8/08 , G11C5/147
摘要： A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator. Along with further specific details of the voltage regulator, a preferred bandgap reference generator is described.
摘要翻译：提供电压调节器用于控制片上电压发生器，其在电荷储存器两端产生升压电压，以供给存储器阵列中的多个字线驱动器的一个输入端。调节器被配置为使得电荷储存器电压将跟踪电源电压，并且电源电压和电荷储存器电压之间的差将在预定义的电源范围内保持基本上恒定。电压调节器包括带隙参考发生器，用于从参考电压和电源电压产生转换电压的第一差分电路，用于将电源电压与升压电压进行比较的第一晶体管，用于将转换电压与参考电压和锁存比较器，用于使来自第一和第二晶体管的信号输出相等，以便为片上电压发生器定义一个控制信号。除了电压调节器的进一步具体细节之外，还描述了优选的带隙参考发生器。

4. 发明授权

US5300800A Low leakage substrate plate DRAM cell 失效
标题翻译：低泄漏衬底板DRAM单元
公开(公告)号：US5300800A
公开(公告)日：1994-04-05
申请号：US966893
申请日：1992-10-26
申请人： Gary B. Bronner , Sang H. Dhong , Wei Hwang
发明人： Gary B. Bronner , Sang H. Dhong , Wei Hwang
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10829
摘要： Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor disposed in a trench formed in a semiconductor substrate and an access transistor disposed in a well which is opposite in conductivity type to that of the substrate and a buried oxide collar which surrounds an upper portion of the trench.
摘要翻译：公开了一种动态随机存取存储器（DRAM）单元，其包括设置在形成在半导体衬底中的沟槽中的存储电容器和设置在与衬底的导电类型相反的阱中的存取晶体管和埋入氧化物环，围绕沟槽的上部。

5. 发明授权

US5214603A Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors 失效
标题翻译：折叠的双列，超高密度动态随机存取存储器存储上述堆叠存储电容器
公开(公告)号：US5214603A
公开(公告)日：1993-05-25
申请号：US740758
申请日：1991-08-05
申请人： Sang H. Dhong , Wei Hwang , Lewis M. Terman , Matthew R. Wordeman
发明人： Sang H. Dhong , Wei Hwang , Lewis M. Terman , Matthew R. Wordeman
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10832
摘要： A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

6. 发明授权

US5107459A Stacked bit-line architecture for high density cross-point memory cell array 失效
标题翻译：用于高密度交叉点存储器单元阵列的堆叠式位线结构
公开(公告)号：US5107459A
公开(公告)日：1992-04-21
申请号：US513315
申请日：1990-04-20
申请人： Christopher M. Chu , Sang H. Dhong , Wei Hwang , Nicky C-C. Lu
发明人： Christopher M. Chu , Sang H. Dhong , Wei Hwang , Nicky C-C. Lu
IPC分类号： H01L27/10 , G11C11/401 , G11C11/4097 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10841 , G11C11/4097
摘要： A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.

7. 发明授权

US5292678A Forming a bit line configuration for semiconductor memory 失效
标题翻译：形成半导体存储器的位线配置
公开(公告)号：US5292678A
公开(公告)日：1994-03-08
申请号：US882735
申请日：1992-05-14
申请人： Sang H. Dhong , Wei Hwang
发明人： Sang H. Dhong , Wei Hwang
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L21/265
CPC分类号： H01L27/10805 , H01L27/10829 , Y10S257/907
摘要： A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in a row direction while the word lines run in a column direction. Transfer transistors are designed to be shared with the same drain junction and the same bit line contact in order to save area. A choice of at least two described embodiments are provided. In one embodiment, referred to as the offset bit line structure, the bit lines are constructed by using two layers of interconnection lines to connect the interdigitated cells associated to it. By connecting the bit line contacts and with two different interconnecting layers and in an alternating row order, the true and complement bit lines and will run parallel to both sides of the memory array. In another embodiment, referred to as the side wall bit line structure, the bit lines are constructed by using the conductive side wall spacer rails to connect the interdigitated cells associated to it. By connecting the side wall bit line contacts with two sided-side wall spacer rails in an alternating row order, the true and complement bit lines will run parallel to both sides of the memory array.
摘要翻译：公开了一种用于未来一代高密度半导体存储器设计的新的叉指折叠位线（IFBL）架构。在架构中，基本交叉点存储单元以行和列正交组织以形成阵列矩阵。位线在行方向上运行，而字线在列方向上运行。传输晶体管被设计为与相同的漏极结和相同的位线接触共享，以节省面积。提供了至少两个描述的实施例的选择。在一个实施例中，称为偏移位线结构，位线通过使用两层互连线来连接与其相关联的交叉指示的单元来构造。通过连接位线触点和两个不同的互连层并以交替的行顺序，真和补码位线将平行于存储器阵列的两侧延伸。在称为侧壁位线结构的另一实施例中，位线通过使用导电侧壁间隔轨道来连接与其相关联的叉指式电池而构成。通过以交替的行顺序将侧壁位线触点与双面侧壁间隔轨连接，真和补补位线将平行于存储器阵列的两侧延伸。

8. 发明授权

US5250829A Double well substrate plate trench DRAM cell array 失效
标题翻译：双阱衬底板沟槽DRAM单元阵列
公开(公告)号：US5250829A
公开(公告)日：1993-10-05
申请号：US818668
申请日：1992-01-09
申请人： Gary B. Bronner , Sang H. Dhong , Wei Hwang
发明人： Gary B. Bronner , Sang H. Dhong , Wei Hwang
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/02 , H01L29/78
CPC分类号： H01L27/10829
摘要： A high density substrate plate DRAM cell memory device and process are described in which a buried well region is formed adjacent to deep trench capacitors such that the substrate region of DRAM transfer FETs can be electrically isolated from other FETs on a semiconductor substrate. The buried region is partially formed by ion implantation and diffusion to intersect the walls of the deep trenches.
摘要翻译：描述了高密度衬底板DRAM单元存储器件和工艺，其中与深沟槽电容器相邻形成掩埋阱区，使得DRAM转移FET的衬底区域可以与半导体衬底上的其它FET电隔离。掩埋区域通过离子注入和扩散部分形成，以与深沟槽的壁相交。

9. 发明授权

US5157634A DRAM having extended refresh time 失效
标题翻译： DRAM延长了刷新时间
公开(公告)号：US5157634A
公开(公告)日：1992-10-20
申请号：US602037
申请日：1990-10-23
申请人： Sang H. Dhong , Robert L. Franch , Wei Hwang
发明人： Sang H. Dhong , Robert L. Franch , Wei Hwang
IPC分类号： G11C11/401 , G11C11/406 , G11C29/00 , G11C29/04
CPC分类号： G11C11/406
摘要： A DRAM is described including a plurality of operable storage cells, each cell including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a minority of the operable cells, it dissipates below the acceptable level after a shorter time interval T2. The time between DRAM refresh cycles is adjusted so as to be greater than time interval T2. The DRAM comprises: a plurality of redundant storage cells; a decoder for receiving the address of an operable memory cell and providing a first output if the address indicates one of the operable cells of the minority of cells and a second output if the address indicates one of the operable cells of the majority. A switching circuit is responsive to the first output to enable access of a redundant stoarge cell and to prevent access of the minority storage cell. In a preferred embodiment, the redundant storage cells are configured as static storage circuits.
摘要翻译：描述了包括多个可操作的存储单元的DRAM，每个单元包括用于存储指示数据的电荷的电容。对于大多数可操作单元，对于大多数可操作单元，对于少数可操作单元，电荷趋于在预定时间间隔T1之后消散到可接受的水平以下，在更短的时间间隔T2之后，其消耗低于可接受的水平。 DRAM刷新周期之间的时间被调整为大于时间间隔T2。 DRAM包括：多个冗余存储单元; 解码器，用于接收可操作存储器单元的地址，并且如果地址指示少数单元的可操作单元中的一个，并且如果地址指示多数的可操作单元之一，则提供第一输出。开关电路响应于第一输出以使得能够访问冗余的存储单元并且防止少数存储单元的访问。在优选实施例中，冗余存储单元被配置为静态存储电路。

10. 发明授权

US5541887A Multiple port cells with improved testability 失效
标题翻译：多端口单元具有改进的可测试性
公开(公告)号：US5541887A
公开(公告)日：1996-07-30
申请号：US375025
申请日：1995-01-19
申请人： Sang H. Dhong , Wei Hwang , Toshiaki Kirihata
发明人： Sang H. Dhong , Wei Hwang , Toshiaki Kirihata
IPC分类号： G11C8/16 , G11C29/50 , G11C7/00
CPC分类号： G11C29/50 , G11C8/16
摘要： Sequentially terminated write enable pulses applied to respective input ports of a multi-port memory cell is effective to establish a priority among those input ports and provide unconditionally unambiguous writing to a memory cell when write operations are concurrently attempted at two or more ports of that cell, as may be encountered during rigorous testing procedures. Memory structure, particularly that of the input port circuits, is simplified and operational speed is enhanced since signal propagation through a comparator or logic circuit is avoided. Time required for testing of large memory arrays is also significantly reduced.
摘要翻译：施加到多端口存储器单元的相应输入端口的顺序终止写入使能脉冲对于在这些输入端口之间建立优先级是有效的，并且当在该单元的两个或更多个端口同时尝试写入操作时，向存储器单元提供无条件地明确的写入，如在严格的测试程序中可能遇到的。存储器结构，特别是输入端口电路的存储器结构被简化，并且由于避免了通过比较器或逻辑电路的信号传播，因此提高了操作速度。大型存储器阵列测试所需的时间也大大减少。

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