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1. 发明授权

US06219822B1 Method and system for tuning of components for integrated circuits 失效
标题翻译：用于集成电路组件调谐的方法和系统
公开(公告)号：US06219822B1
公开(公告)日：2001-04-17
申请号：US09129717
申请日：1998-08-05
申请人： George D. Gristede , Wei Hwang , Christophe Robert Tretz
发明人： George D. Gristede , Wei Hwang , Christophe Robert Tretz
IPC分类号： H03K1900
CPC分类号： G06F17/505
摘要： A method for automatically tuning object sizes in an integrated circuit includes the steps of providing a circuit having objects disposed therein, inputting equations associated with the objects to provide a relationship between a size of the object and timing information of signals transmitted between the objects, extracting transition times of the signals transmitted between objects by simulating the circuit in operation by evaluating the equations and adjusting the sizes of the objects in the circuit according to the timing information and the transition times until user defined criteria are achieved for the circuit. Systems are also provided to carry out the method.
摘要翻译：一种用于在集成电路中自动调谐对象尺寸的方法包括以下步骤：提供具有设置在其中的对象的电路，输入与对象相关联的方程，以提供对象的大小与在对象之间传输的信号的定时信息之间的关系，提取通过在运行中模拟电路的运算中的信号的转换时间，并根据定时信息和转换时间调整电路中的对象的大小，直到电路达到用户定义的标准。还提供系统来执行该方法。

2. 发明授权

US06175949B1 Method and system for selecting sizes of components for integrated circuits 失效
标题翻译：集成电路组件尺寸选择方法及系统
公开(公告)号：US06175949B1
公开(公告)日：2001-01-16
申请号：US09046826
申请日：1998-03-24
申请人： George D. Gristede , Wei Hwang , Christophe Robert Tretz
发明人： George D. Gristede , Wei Hwang , Christophe Robert Tretz
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A method of automatically selecting object size in an integrated circuit includes the steps of providing a circuit topology having objects disposed therein, inputting equations associated with the objects to provide sizing adjustment for the objects, assigning parameter values in the equations based on physical constraints of the circuit for one or more objects, selecting one or more objects to be sized, evaluating cones of influence for the objects selected to identify influenced objects influenced by a change in the selected object and computing for each selected object and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit. A system for performing the method of the present invention is also described.
摘要翻译：一种在集成电路中自动选择对象尺寸的方法包括以下步骤：提供具有设置在其中的对象的电路拓扑，输入与对象相关联的方程，以提供对象的尺寸调整，基于物体的物理约束来分配等式中的参数值一个或多个对象的电路，选择一个或多个对象以确定大小，评估被选择用于识别受所选择的对象的变化影响的受影响对象的影响的影响的锥体，以及针对每个所选择的对象和受影响的对象的计算，具有相关联的方程，直到为电路实现用户定义的准则。还描述了用于执行本发明的方法的系统。

3. 发明授权

US07389481B2 Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells 有权
标题翻译：集成电路设计利用功能可互换的动态逻辑单元阵列
公开(公告)号：US07389481B2
公开(公告)日：2008-06-17
申请号：US11128069
申请日：2005-05-12
申请人： Christophe Robert Tretz
发明人： Christophe Robert Tretz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H03K19/1736 , H03K19/1772
摘要： A circuit arrangement, integrated circuit device, apparatus, program product, and method utilize an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output as a function of a plurality of inputs, and an output latch that is configured to latch the output generated by the logic circuit. The array of functionally interchangeable dynamic logic cells are used to implement an application specific logic function within a specific logic design by routing a plurality of conductors between inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells.
摘要翻译：电路装置，集成电路装置，装置，程序产品和方法利用功能上可互换的动态逻辑单元的阵列来实现集成电路设计中的专用逻辑功能。每个功能可互换的动态逻辑单元包括被配置为产生作为多个输入的函数的输出的动态逻辑电路和被配置为锁存由逻辑电路产生的输出的输出锁存器。功能可互换的动态逻辑单元的阵列用于通过在功能上可互换的动态逻辑单元的至少一个子集的输入和输出之间路由多个导体来在特定逻辑设计中实现特定于应用的逻辑功能。

4. 发明申请

US20080189663A1 INTEGRATED CIRCUIT DESIGN UTILIZING ARRAY OF FUNCTIONALLY INTERCHANGEABLE DYNAMIC LOGIC CELLS 有权
标题翻译：集成电路设计利用功能可互换的动态逻辑电池阵列
公开(公告)号：US20080189663A1
公开(公告)日：2008-08-07
申请号：US12061155
申请日：2008-04-02
申请人： Christophe Robert Tretz
发明人： Christophe Robert Tretz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H03K19/1736 , H03K19/1772
摘要： A method utilizes an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output as a function of a plurality of inputs, and an output latch that is configured to latch the output generated by the logic circuit. The array of functionally interchangeable dynamic logic cells are used to implement an application specific logic function within a specific logic design by routing a plurality of conductors between inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells.
摘要翻译：一种方法利用功能可互换的动态逻辑单元的阵列来实现集成电路设计中的专用逻辑功能。每个功能可互换的动态逻辑单元包括被配置为产生作为多个输入的函数的输出的动态逻辑电路和被配置为锁存由逻辑电路产生的输出的输出锁存器。功能可互换的动态逻辑单元的阵列用于通过在功能上可互换的动态逻辑单元的至少一个子集的输入和输出之间路由多个导体来在特定逻辑设计中实现特定于应用的逻辑功能。

5. 发明授权

US07268590B2 Method and apparatus for implementing subthreshold leakage reduction in LSDL 有权
标题翻译：在LSDL中实现亚阈值泄漏减少的方法和装置
公开(公告)号：US07268590B2
公开(公告)日：2007-09-11
申请号：US11304142
申请日：2005-12-15
申请人： Jerry C. Kao , Chung-Tao Li , Salvatore Nicholas Storino , Christophe Robert Tretz
发明人： Jerry C. Kao , Chung-Tao Li , Salvatore Nicholas Storino , Christophe Robert Tretz
IPC分类号： H03K19/096
CPC分类号： H03K19/0013
摘要： A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.
摘要翻译：提供了一种用于在限制开关动态逻辑（LSDL）中实现亚阈值泄漏电流降低的方法和装置。有限开关动态逻辑电路包括交叉耦合NAND和反相器逻辑。动态节点为NAND提供第一个输入。睡眠信号为NAND提供第二输入。 NAND的输出为反相器逻辑提供反相NAND输出并提供互补输出的输入。 NAND逻辑包括接收睡眠输入的串联连接的第一睡眠晶体管。在睡眠模式期间，第一睡眠晶体管被关闭。第二个睡眠晶体管连接在电源轨和NAND输出之间。在休眠模式期间，第二个睡眠晶体管导通，以强制NAND输出并强制低互补输出。

6. 发明授权

US07954077B2 Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells 有权
标题翻译：集成电路设计利用功能可互换的动态逻辑单元阵列
公开(公告)号：US07954077B2
公开(公告)日：2011-05-31
申请号：US12061155
申请日：2008-04-02
申请人： Christophe Robert Tretz
发明人： Christophe Robert Tretz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H03K19/1736 , H03K19/1772
摘要： A method utilizes an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output as a function of a plurality of inputs, and an output latch that is configured to latch the output generated by the logic circuit. The array of functionally interchangeable dynamic logic cells are used to implement an application specific logic function within a specific logic design by routing a plurality of conductors between inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells.
摘要翻译：一种方法利用功能可互换的动态逻辑单元的阵列来实现集成电路设计中的专用逻辑功能。每个功能可互换的动态逻辑单元包括被配置为产生作为多个输入的函数的输出的动态逻辑电路和被配置为锁存由逻辑电路产生的输出的输出锁存器。功能可互换的动态逻辑单元的阵列用于通过在功能上可互换的动态逻辑单元的至少一个子集的输入和输出之间路由多个导体来在特定逻辑设计中实现特定于应用的逻辑功能。

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