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31. 发明授权

US06825698B2 Programmable high speed I/O interface 有权
标题翻译：可编程高速I / O接口
公开(公告)号：US06825698B2
公开(公告)日：2004-11-30
申请号：US10229342
申请日：2002-08-26
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03B100
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

32. 发明授权

US07200769B1 Self-compensating delay chain for multiple-date-rate interfaces 有权
标题翻译：多速率接口的自补偿延迟链
公开(公告)号：US07200769B1
公开(公告)日：2007-04-03
申请号：US10037861
申请日：2002-01-02
申请人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
发明人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
IPC分类号： G06F1/04
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C2207/108 , H03L7/0805 , H03L7/0814 , H03L7/091
摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.
摘要翻译：用于延迟多数据速率接口的时钟信号的方法和装置。一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

33. 发明授权

US07725755B1 Self-compensating delay chain for multiple-date-rate interfaces 有权
标题翻译：多速率接口的自补偿延迟链
公开(公告)号：US07725755B1
公开(公告)日：2010-05-25
申请号：US11668353
申请日：2007-01-29
申请人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
发明人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
IPC分类号： G06F1/00 , G06F1/14
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C2207/108 , H03L7/0805 , H03L7/0814 , H03L7/091
摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.
摘要翻译：用于延迟多数据速率接口的时钟信号的方法和装置。一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

34. 发明授权

US07215143B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07215143B1
公开(公告)日：2007-05-08
申请号：US11000472
申请日：2004-11-29
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948 , H03K17/00
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

35. 发明授权

US06853215B1 Programmable I/O element circuit for high speed logic devices 失效
标题翻译：用于高速逻辑器件的可编程I / O元件电路
公开(公告)号：US06853215B1
公开(公告)日：2005-02-08
申请号：US10685355
申请日：2003-10-09
申请人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
发明人： Khai Nguyen , Chiakang Sung , Bonnie Wang , Joseph Huang , Phillip Pan , In Whan Kim , Gopi Rangan , Yan Chong , Xiaobao Wang , Tzung-Chin Chang
IPC分类号： C07K14/47 , C07K16/28 , H03K19/173
CPC分类号： C07K16/28 , A61K2039/505 , C07K14/47
摘要： A programmable I/O element for an I/O terminal of a logic array is suitable for operating according to high speed 110 modes such as double data rate and zero bus turnaround. The I/O element may include an input block with two registers for registering input signals from the terminal upon alternate clock edges. In addition or alternatively, it may include an output block with two registers that separately register output signals from the array on the same clock edge and a multiplexer that alternately outputs those signals. For bidirectional terminals, the multiplexer output is connectable to the I/O terminal via an output buffer, and an output enable block provides an enable signal to a gating input of the output buffer. Programmable delays may be included in the input, output, and output enable paths, in particular to provide a slower turn-on time than turn-off time for the output buffer.
摘要翻译：用于逻辑阵列的I / O端子的可编程I / O元件适用于根据高速110模式（例如双数据速率和零总线周转）进行操作。 I / O元件可以包括具有两个寄存器的输入块，用于在备用时钟边缘上从终端注册输入信号。另外或替代地，它可以包括具有两个寄存器的输出块，该两个寄存器在相同的时钟沿上单独地寄存来自阵列的输出信号，以及交替地输出这些信号的多路复用器。对于双向端子，多路复用器输出可通过输出缓冲器连接到I / O端子，并且输出使能块向输出缓冲器的选通输入提供使能信号。可编程延迟可以包括在输入，输出和输出使能路径中，特别是提供比输出缓冲器的关断时间更慢的导通时间。

36. 发明授权

US06766505B1 Parallel programming of programmable logic using register chains 有权
标题翻译：使用寄存器链的可编程逻辑的并行编程
公开(公告)号：US06766505B1
公开(公告)日：2004-07-20
申请号：US10106675
申请日：2002-03-25
申请人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
发明人： Gopi Rangan , Khai Nguyen , Chiakang Sung , Xiaobao Wang , In Whan Kim , Yan Chong , Philip Pan , Joseph Huang , Bonnie Wang
IPC分类号： G06F1750
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17764 , Y02T10/82
摘要： Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register includes two or more serial register chains, each chain being made up of a serial chain of registers. The configuration data is input into the two of more chains of the data registers in parallel. Circuitry is also provided to handle redundancy.
摘要翻译：技术和电路用于更快速地配置可编程集成电路。配置数据通过并行输入（705）并行输入到可编程集成电路中，并且该数据也在内部并行处理。配置数据将被存储在数据寄存器（722）中。该数据寄存器包括两个或多个串行寄存器链，每个链由串行寄存器组成。配置数据并行输入数据寄存器的两个链中。还提供电路来处理冗余。

37. 发明授权

US07425844B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07425844B1
公开(公告)日：2008-09-16
申请号：US11697299
申请日：2007-04-06
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948 , H03K17/00
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

38. 发明授权

US06992947B1 Dual-port SRAM in a programmable logic device 失效
公开(公告)号：US06992947B1
公开(公告)日：2006-01-31
申请号：US10696209
申请日：2003-10-28
申请人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong
发明人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong
IPC分类号： G11C8/00
CPC分类号： H03K19/1776 , G11C8/16
摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

39. 发明授权

US06911860B1 On/off reference voltage switch for multiple I/O standards 有权
标题翻译：用于多个I / O标准的开/关参考电压开关
公开(公告)号：US06911860B1
公开(公告)日：2005-06-28
申请号：US10037716
申请日：2001-11-09
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Bonnie Wang , Philip Pan , Yan Chong , In Whan Kim , Gopinath Rangan , Tzung-Chin Chang
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Bonnie Wang , Philip Pan , Yan Chong , In Whan Kim , Gopinath Rangan , Tzung-Chin Chang
IPC分类号： H03K17/35
CPC分类号： H03K17/6871 , H03K3/356113 , H03K17/063
摘要： A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.
摘要翻译：开关电路选择性地将某些I / O标准所需的参考电压提供给逻辑器件。该电路接收与设备的I / O电源不同的专用电源。其还可以包括电平移位电路，用于将具有由第一电源确定的逻辑电平的主控制信号转换成具有由专用电源确定的逻辑电平的第一控制信号。开关电路还包括传输开关，其响应于至少第一控制信号将参考电压传递到输出。传输开关可以是CMOS传输门，其中至少一个NMOS晶体管由第一控制信号控制，与由与第一控制信号互补的第二控制信号控制的至少一个PMOS晶体管并联。第二控制信号可以由另一电平移位电路产生并具有由I / O电源确定的逻辑电平。

40. 发明授权

US06731142B1 Circuit for providing clock signals with low skew 有权
标题翻译：提供低偏移时钟信号的电路
公开(公告)号：US06731142B1
公开(公告)日：2004-05-04
申请号：US10412705
申请日：2003-04-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Xiaobao Wang , In Whan Kim , Gopi Rangan , Yan Chong , Phillip Pan , Tzung-Chin Chang
IPC分类号： H03K2100
CPC分类号： H03M9/00 , G06F1/08 , H03K5/135
摘要： A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.
摘要翻译：公开了一种数字，优选可编程的电路，用于提供具有可变频率和/或相位的一个或多个时钟信号。时钟信号相对于由该电路提供的其它时钟信号和数据信号呈现低的偏移量。在一个实施例中，电路包括多个通道，每个通道具有并行/串行输出移位寄存器，触发器和延迟电路。移位寄存器可以在分频时钟通道中的数据通道或时钟频率选择位中接收数据位。来自寄存器的串行输出用作触发器的输入，两者均由输入参考时钟触发。延迟电路延迟输入参考时钟。在每个通道中，多路复用器被配置为选择从寄存器，触发器和延迟电路输出输出的时钟或数据通道。由于所有输出路径中的延迟相匹配，所以偏斜最小化。

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